34C60 Datasheet, PDF (16/58 Pages) SMSC Corporation – PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE

3.3 Device Addressing
The Bi-Directional Parallel Peripheral Interface protocol, defined by the IEEE STD 1284 (Reference 1), describes two basic
types of 8-bit information transfers: data read/write operations and address read/write operations. The PPC34C60's bus
and internal registers are accessed via data read/write operations.
The PPC34C60's address mode is set through an SPP, EPP, or ECP address write operation. Table 1 specifies the control
signals used by each protocol to perform Address and Data Cycles and to indicate reverse data flow. Refer to the IEEE
STD 1284 (Reference 1) for further information.
SIGNAL
Address
Strobe
Data
Strobe
Reverse Channel
Signal
Table 1 - Key Address/Data Cycle Signals
SPP
EPP
SEL
SEL
STB
ALF
INIT=0
IMPLICIT
ECP
STB(ALF=0)
STB(ALF=1)
INIT = 0
The Parallel Port provides a byte-wide parallel data path. FIGURE 4 defines the data bits of this parallel port data path
during an address write operation to the PPC34C60.
D7 D6 D5 D4 D3 D2 D1 D0
1
W
B MA
A
A
A
Bus or Register Address
Type of Access
Write/Read
Required for ECP
FIGURE 4 - PARALLEL PORT ADDRESS WRITE AND DATA BITS
SMSC DS – PPC34C60
Page 16
ADVANCED INFORMATION
Rev. 06/01/2001