FDC37C669 Datasheet, PDF (157/164 Pages) SMSC Corporation – PC 98/99 COMPLIANT SUPER I/O FLOPPY DISK CONTROLLER WITH INFRARED SUPPORT

ECP PARALLEL PORT TIMING
Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the
peak 500 Kbps allowed in the forward direction
using DMA. The state machine does not
examine nAck and begins the next transfer
based on Busy. Refer to Figure 19.
peripheral then accepts the data and sets
PeriphAck (Busy) low, completing the transfer.
This sequence is shown in Figure 20.
The timing is designed to provide 3 cable
round-trip times for data setup if Data is driven
simultaneously with HostClk (nStrobe).
ECP Parallel Port Timing
Reverse-Idle Phase
The timing is designed to allow operation at
approximately 2.0Mbytes/sec over a 15ft cable.
If a shorter cable is used then the bandwidth will
increase.
Forward-Idle
When the host has no data to send it keeps
HostClk (nStrobe) high and the peripheral
will leave PeriphClk (Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands
from the host to the peripheral using an
interlocked PeriphAck and HostClk. The
peripheral may indicate its desire to send data
to the host by asserting nPeriph Request.
The Forward Data Transfer Phase may be
entered from the Forward-Idle Phase. While in
the Forward Phase the peripheral may
asynchronously assert the nPeriph Request
(nFault) to request that the channel be reversed.
When the peripheral is not busy it sets
PeriphAck (Busy) low. The host then sets
HostClk (nStrobe) low when it is prepared to
send data. The data must be stable for the
specified setup time prior to the falling edge of
HostClk. The peripheral then sets PeriphAck
(Busy) high to acknowledge the handshake. The
host then sets HostClk (nStrobe) high. The
The peripheral has no data to send and keeps
PeriphClk high. The host is idle and keeps
HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands
from the peripheral to the host using an
interlocked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be
entered from the Reverse-Idle Phase. After the
previous byte has beed accepted the host sets
HostAck (nAutoFd) low. The peripheral then
sets PeriphClk (nAck) low when it has data
to send. The data must be stable for the
specified setup time prior to the falling edge of
PeriphClk. When the host is ready it to accept a
byte it sets. HostAck (nAutoFd) high to
acknowledge the handshake. The peripheral
then sets PeriphClk (nAck) high. After the host
has accepted the data it sets HostAck (nAutoFd)
low, completing the transfer. This sequence is
shown in Figure 21.
OutputDrivers
To facilitate higher performance data transfer,
the use of balanced CMOS active drivers for
critical signals (Data, HostAck, HostClk,
PeriphAck, PeriphClk) are used ECP Mode.
Because the use of active drivers can present
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