LPC47M112_07 Datasheet, PDF (154/204 Pages) SMSC Corporation – Enhanced Super I/O Controller with LPC Interface

Enhanced Super I/O Controller with LPC Interface
Datasheet
Note 2: The IRTX2 function can be used on this pin if the IR Location Mux bit in the Serial Port 2 IR Option register
is set
Note 3: These pins default to an output and LOW on VCC POR and Hard Reset.
Note 4: If the FDC function is selected on this pin (nMTR1, nDS1, DRVDEN0, DRVDEN1) then bit 6 of the FDD
Mode Register (Configuration Register 0xF0 in Logical Device 0) will override bit 7 in the GPIO Control
Register. Bit 7 of the FDD Mode Register will also affect the pin if the FDC function is selected.
Note 5: The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the SMI enable bit
(EN_SMI, bit 7 of the SMI_EN2 register) is ‘0’. When the output buffer type is OD, nIO_SMI pin is floating
when inactive; when the output buffer type is push-pull, the nIO_SMI pin is high when inactive.
Note 6: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on
a VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI
status bits will be set on a VCC POR since these pins revert to their non-inverting GPIO output function
when VCC is removed from the part. These GPIOs cannot be used for PME wakeup when the part is under
VTR power (VCC=0).
Note 7: These bits are R/W but have no effect on circuit operation.
SMSC DS – LPC47M112
Page 154
DATASHEET
Rev. 02-16-07