FDC37B727-NS Datasheet, PDF (144/238 Pages) SMSC Corporation – 128 Pin Enhanced Super I/O Controller with ACPI Support

respective enable bit in the enable register is
marked as reserved for these special cases.
The enable registers allow the setting of the
status bit to generate an interrupt. As a general
rule there is an enable bit in the enable register
for every status bit in the status register. The
control register provides special controls for the
associated event, or special control features that
are not associated with an interrupt event. The
ordering of a register block is the status
registers, followed by enable registers, followed
by control registers.
Table 60 and 61 list the PM1/GPE and
PME/SMI/MSC register blocks and the locations
of the registers contained in these blocks. All of
these registers are powered by VTR and battery
backed-up and are reset on Vbat POR.
Wakeup Event Configuration is Retained by
Battery Power
To preserve the configuration of the wakeup
functions that were programmed prior to the loss
of Vtr upon its return, the soft power
management registers, PME, SCI, SMI registers
and GPIO registers are all powered by the
battery. These registers are reset to their default
values only on Vbat POR. These registers are
described in the sections below.
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