PAC1720 Datasheet, PDF (14/47 Pages) SMSC Corporation – Dual High-Side Current Sense Monitor with Power Calculation

Dual High-Side Current Sense Monitor with Power Calculation
Datasheet
Chapter 3 Communications
3.1
System Management SMBus Interface Protocol
The PAC1720 communicates with a host controller through the SMBus. The SMBus is a two-wire serial
communication protocol between a computer host and its peripheral devices. A detailed timing diagram
is shown in Figure 3.1. Stretching of the SMCLK signal is supported; however, the PAC1720 will not
stretch the clock signal.
T _LOW
T _HIGH
SMCLK
SMDATA
T_BUF
T _RISE
T _HD:STA ^T HD:DAT
T _FALL
T _SU:DAT
P
S
S - Start Condition
T _HD:STA
T _SU:STO
T _SU:STA
S
P - Stop Condition
P
3.1.1
3.1.2
Figure 3.1 SMBus Timing Diagram
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by a 1-bit RD / WR indicator. If
this RD / WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD / WR bit
is a logic ‘1’, the SMBus host is reading data from the client device.
The PAC1720 SMBus address is determined by a single resistor connected between ground and the
ADDR_SEL pin as shown in Table 3.1.
Revision 1.1 (12-08-11)
14
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