EMC2305_11 Datasheet, PDF (14/56 Pages) SMSC Corporation – Multiple RPM-Based PWM Fan Controller for Five Fans

Multiple RPM-Based PWM Fan Controller for Five Fans
Datasheet
PULL-UP RESISTOR
4.7k Ohm ±5%
6.8k Ohm ±5%
10k Ohm ±5%
15k Ohm ±5%
22k Ohm ±5%
33k Ohm ±5%
Table 3.1 ADDR_SEL Pin Decode
SMBUS ADDRESS
0101_110(r/w)
0101_111(r/w)
0101_100(r/w)
0101_101(r/w)
1001_100(r/w)
1001_101(r/w)
ADDITIONAL FUNCTIONS
None - CLK pin used as clock input
or output
CLK pin used to determine default
fan drive - see Section 4.5.1. The
CLK pin cannot be used as a clock
input or output
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it
matches and the ARA address if the ALERT# pin is asserted). This is done by the client device pulling
the SMBus Data line low after the 8th bit of each byte that is transmitted.
The Host will NACK (not acknowledge) the data received from the client by holding the SMBus data
line high after the 8th data bit has been sent.
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC2305 detects an SMBus Stop
bit has been communicating with the SMBus protocol, it will reset its client interface and prepare to
receive further communications.
SMBus Time-out
The EMC2305 includes an SMBus timeout feature. Following a 30ms period of inactivity on the
SMBus, the device will time-out and reset the SMBus interface.
The SMBus timeout feature is disabled by default and can be enabled via clearing the DIS_TO bit in
the Configuration register (20h).
SMBus and I²C Compliance
The major difference between SMBus and I²C devices is highlighted here. For complete compliance
information refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz (I²C has no minimum frequency).
2. The slave protocol will reset if the clock is held low for longer than 30ms (I²C has no timeout).
3. The slave protocol will reset if both the clock and data lines are held high for longer than 150us.
4. I²C devices do not support the Alert Response Address functionality (which is optional for SMBus).
Revision 1.3 (05-18-11)
14
DATASHEET
SMSC EMC2305