FDC37B80X Datasheet, PDF (136/194 Pages) SMSC Corporation – PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up

Table 54 - Chip Level Registers
REGISTER
ADDRESS
DESCRIPTION
OSC
Default = 0x04, on
Vcc POR or
Reset_Drv hardware
signal.
0x24 R/W
Bit[0] Reserved
Bit [1] PLL Control
= 0 PLL is on (backward Compatible)
= 1 PLL is off
Bits[3:2] OSC
= 01 Osc is on, BRG clock is on.
= 10 Same as above (01) case.
= 00 Osc is on, BRG Clock Enabled.
= 11 Osc is off, BRG clock is disabled.
STATE
C
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0 12-Bit Address Qualification
= 1 16-Bit Address Qualification
Bit[7] Reserved
Chip Level
Vendor Defined
0x25 Reserved - Writes are ignored, reads return 0.
Configuration
0x26 Bit[7:1] Configuration Address Bits [7:1]
C
Address Byte 0
Bit[0] = 0
See Note 1
Default
=0xF0 (Sysopt=0)
=0x70 (Sysopt=1)
on Vcc POR or
Reset_Drv
Configuration
0x27 Bit[7:0] Configuration Address Bits [15:8]
C
Address Byte 1
See Note 1
Default = 0x03
on Vcc POR or
Reset_Drv
Default = 0x00
on VCC POR and
Hard Reset
Chip Level
Vendor Defined
0x28
Bits[7:0] Reserved - Writes are ignored, reads
return 0.
0x29 -0x2A Reserved - Writes are ignored, reads return 0.
TEST 4
0x2B R/W Test Modes: Reserved for SMSC. Users should not
C
write to this register, may produce undesired
Default = 0x00, on
results.
Vcc POR
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