LAN9220_12 Datasheet, PDF (131/151 Pages) SMSC Corporation – 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
6.4
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Parameters t_csh and t_csl must be extended using wait states to meet the t_cycle minimum.
PIO Burst Reads
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
A[7:5]
A[4:1]
nCS, nRD
Data Bus
Figure 6.3 PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 16 bits
SYMBOL
t_csh
t_csdv
t_acyc
t_asu
t_adv
t_ah
t_don
t_doff
t_doh
Table 6.4 PIO Burst Read Timing
DESCRIPTION
MIN
nCS, nRD Deassertion Time
13
nCS, nRD Valid to Data Valid
Address Cycle Time
165
Address Setup to nCS, nRD valid
0
Address Stable to Data Valid
Address Hold Time
0
Data Buffer Turn On Time
0
Data Buffer Turn Off Time
Data Output Hold Time
0
TYP
MAX UNITS
ns
30
ns
ns
40
ns
ns
Note 6.3
ns
ns
Note 6.3 When VDDVARIO is 3.3V or 2.5V, the maximum T_doff time is 7ns. When VDDVARIO is
1.8V, the maximum T_doff time is 9ns.
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
SMSC LAN9220
131
DATASHEET
Revision 2.9 (03-01-12)