USB2005 Datasheet, PDF (12/21 Pages) SMSC Corporation – USB2.0 ATA/ATAPI CONTROLLER WITH PD - DRM

RESET input
Test input
USB2.0 ATA/ATAPI Controller with PD-DRM
Table 5.1 USB2005 Pin Descriptions (continued)
Datasheet
nRESET
IS
nTest[0:2]
IP
This active low signal is used by the system to
reset the chip. The active low pulse should be
at least 100ns wide.
These signals are used for testing the chip.
User should normally leave them unconnected.
For board continuity testing, all pads (except
RBIAS, FSDP, USBDP, USBDM, FSDM,
RTERM, XTAL1, XTAL2, LOOPFLTR and
nTEST[0:2]) are included in an XNOR chain
which is enabled by pulling nTEST2 low. nIOR
is the output of the chain (the chain begins at
pin 2) and will reflect the toggling of a signal
on each pin. Circuit board continuity of the pin
solder connections after assembly can be
checked in this manner
POWER, GROUNDS, AND NO CONNECTS
VDD
VDDIO
VDDP
VSSP
VDDA
VSSA
GND
NC
+2.5V Core power
+3.3V I/O power
+2.5 Analog power
Analog Ground Reference
+3.3V Analog power
Analog Ground Reference
Ground Reference
No Connect. These pins should not be
connected externally.
5.1
Buffer Type Descriptions
Table 5.2 USB2005 Buffer Type Descriptions
BUFFER
I
IS
IP
IO8
O8
O12
IO12PU
IO12
IO20
O20
O20PU
DESCRIPTION
Input
Input with Schmitt trigger
Input with weak pull-up
Input/Output with 8 mA drive
Output with 8mA drive
Output with 12mA drive
Input/Output with 12 ma drive and controlled weak pull up
Input/Output with 12 ma drive
Input/output with 20mA drive
Output with 20mA drive
Output with 20mA drive and weak pullup
Revision 0.2 (06-07-05)
12
DATASHEET
SMSC USB2005