FDC37M81 Datasheet, PDF (107/198 Pages) SMSC Corporation – PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up

Register Behavior
Table 43 illustrates the AT and PS/2 (including
Model 30) configuration registers available and
the type of access permitted. In order to
maintain software transparency, access to all
the registers must be maintained. As Table 43
shows, two sets of registers are distinguished
based on whether their access results in the part
remaining in powerdown state or exiting it.
Access to all other registers is possible without
awakening the part. These registers can be
accessed during powerdown without changing
the status of the part. A read from these
registers will reflect the true status as shown in
the register description in the FDC description. A
write to the part will result in the part retaining
the data and subsequently reflecting it when the
part awakens. Accessing the part during
powerdown may cause an increase in the power
consumption by the part. The part will revert
back to its low power mode when the access
has been completed.
Pin Behavior
The FDC37M81x is specifically designed for
systems in which power conservation is a
primary concern. This makes the behavior of
the pins during powerdown very important.
The pins of the FDC37M81x can be divided into
two major categories: system interface and
floppy disk drive interface. The floppy disk drive
pins are disabled so that no power will be drawn
through the part as a result of any voltage
applied to the pin within the part's power supply
range. Most of the system interface pins are left
active to monitor system accesses that may
wake up the part.
System Interface Pins
Table 44 gives the state of the system interface
pins in the powerdown state. Pins unaffected by
the powerdown are labeled "Unchanged". Input
pins are "Disabled" to prevent them from
causing currents internal to the FDC37M81x
when they have indeterminate input values.
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