LPC47M14X Datasheet, PDF(105/205 Page) SMSC Corporation – 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB

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LPC47M14X Datasheet, PDF (105/205 Pages) SMSC Corporation – 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB

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6.13.6 Register Definitions

Host I/F Data Register

The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard

Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the

Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for

more information.

Host I/F Status Register

The Status register is 8 bits wide.

Table 52 shows the contents of the Status register.

Table 52 â Status Register

C/D

IBF

OBF

Status Register

This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M14x CPU.

UD Writable by LPC47M14x CPU. These bits are user-definable.

C/D (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 =

command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 =

IBF (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register.

Setting this flag activates the LPC47M14x CPU's nIBF (MIRQ) interrupt if enabled. When the LPC47M14x CPU

reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no

output pin associated with this internal signal.

OBF (Output Buffer Full) - This flag is set to whenever the LPC47M14x CPU write to the output data register (DBB).

When the host system reads the output data register, this bit is automatically reset.

6.13.7 External Clock Signal

The LPC47M14x Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset

pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR)

and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.

6.13.8 Default Reset Conditions

The LPC47M14x has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 53 for

the effect of each type of reset on the internal registers.

Table 53 â Resets

DESCRIPTION

KCLK

KDAT

MCLK

MDAT

Host I/F Data Reg

Host I/F Status Reg

HARDWARE RESET

(PCI_RESET#)

Low

N/A

00H

N/A: Not Applicable

GATEA20 AND KEYBOARD RESET

The LPC47M14x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and

KRESET and Port 92 Fast GateA20 and KRESET.

SMSC DS â LPC47M14X

Page 105

Rev. 03/19/2001

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