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LV244 Datasheet, PDF (4/4 Pages) System Logic Semiconductor – OCTAL BUFFER/LINE DRIVE; 3-STATE
SL74LV244
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=6.0 ns)
Symbol
Parameter
Test
VCC
Guaranteed Limit
conditions
V
25°C
-40°C to
85°C
125°C
Unit
min max min max min max
tPHL, tPLH Propagation delay , 1An VI = 0 V or VCC 1.2 - 100 -
125
-
150
ns
to 1Yn, 2An to 2Yn
Figure 1 and 3 2.0 - 24 -
30
-
36
* - 15 -
19
-
23
tPHZ tPLZ Propagation delay, 1OE to VI = 0 V or VCC 1.2 - 140 -
175
-
210
ns
1Yn, 2OE to 2Yn
Figure 2 and 4 2.0 - 30 -
35
-
41
* - 20 -
24
-
28
tPZH tPZL Propagation delay, 1OE to VI = 0 V or VCC 1.2 - 140 -
175
-
210
ns
1Yn, 2OE to 2Yn
Figure 2 and 4 2.0 - 32 -
40
-
48
* - 20 -
25
-
30
tTHL, tTLH Output Transition Time, VI = 0 V or VCC 1.2 - 60 -
75
-
90
ns
Any Output
Figure 1 and 3 2.0 - 16 -
20
-
24
* - 10 -
13
-
15
CI Input capacitance
CPD Power dissipation
capacitance (per one
channel)
3.0 - 7.0 - 7.0 - 7.0 pF
VI = 0 V or VCC
- 50 -
-
-
-
pF
* VCC = 3.3 ± 0.3 V
1Anor 2An
tr
90%
10% 50%
tPLH
1Yn or 2Yn
50% 90%
10%
tTLH
tf
tPHL
VCC
GND
tTHL
1OE or 2OE
t PZL
1Ynor 2Y n
t PZH
1Ynor 2Y n
50%
50%
50%
t PLZ
t PHZ
VCC
GND
VCC
VOL
VOH
GND
Figure 1. Switching Waveforms
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*
CL
Figure 2. Switching Waveforms
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
1k
*
CL
Connect to V C C when
testing tP LZ and tP Z L
Connect to GND when
testing tP HZ and tP Z H
* Includes all probe and jig capacitance
Figure 3. Test Circuit
* Includes all probe and jig capacitance
Figure 4. Test Circuit
SLS System Logic
Semiconductor
4