SKY73112 Datasheet, PDF (3/13 Pages) Skyworks Solutions Inc. – 750-850 MHz High Performance VCO/Synthesizer With Integrated Switch

PRELIMINARY DATA SHEET • SKY73112 VCO/SYNTHESIZER
Technical Description
The SKY73112 is a fractional-N frequency synthesizer using a
Σ∆ modulation technique. The fractional-N implementation
provides low in-band noise by having a low division and fast
frequency settling time. The device also provides programmable,
arbitrary fine frequency resolution. This compensates the
frequency synthesizer for crystal frequency drift.
Serial I/O Control Interface
The SKY73112 is programmed through a three-wire serial bus
control interface using four 26-bit words. The three-wire interface
consists of three signals: CLK (pin 17), LE (pin 19), and the bit
serial data line DATA (pin 18). The convention is to load data from
the most significant bit to the least significant bit (MSB to LSB). A
serial data input timing diagram is shown in Figure 3. Preset
timing parameter values are provided in Table 2.
Figure 4 depicts the serial bus, which consists of one 26-bit load
register and four separate 24-bit registers. Data is initially clocked
into the load register starting with the MSB and ending with the
LSB. The LE signal is used to gate the clock to the load register,
requiring the LE signal to be brought low before the data load.
Data is shifted on the rising edge of CLK.
The two final LSBs are decoded to determine which holding
register should latch the data. The falling edge of LE latches the
data into the appropriate holding register. This programming
sequence must be repeated to fill all four holding registers.
Loading new data into a holding register not associated with the
synthesizer frequency programming does not reset or change the
synthesizer. The synthesizer should not lose lock before, during,
or after a new serial word load that does not change the
programmed frequency.
VCO Tuning Loop
A VCO auto-tuning loop provides the proper 7-bit coarse tuning
setting for the VCO switch capacitors in the VCO output. This sets
the oscillation frequency as close to target as possible before
starting fine analog tuning.
The auto-tuning loop is designed to compensate process variation
so that the VCO fine tuning range can be reduced to cover
temperature variation only. The auto-tuning loop reduces VCO
gain (KV), which reduces the VCO phase noise.
VCO Prescalers
The VCO prescalers divide the VCO output signal by either 16/17
or 8/9. The Σ∆ modulator determines whether to divide by 16 or
17 in the 16/17 mode, or whether to divide by 8 or 9 in the 8/9
mode.
N-Counter
The N-counter consists of two asynchronous ripple counters, a
6-bit M-counter and a 4-bit A-counter. The M-counter determines
the counts using the lower division ratio in the prescaler (8 or 16);
the A-counter determines the counts using the upper division ratio
(9 or 17).
By changing the counter setting at each reference clock cycle, the
Modulated Fractional Divider (MFD) achieves the desired noise
shaping.
DATA
CLK
LE
tDHD
tCKH
tDSU
tCKL
tCLE
tLEC
tLEW
S1053
Figure 3. SKY73112 Serial Data Input Timing Diagram (MSB First)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
200736A • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • July 9, 2007
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