SKY12340-364LF Datasheet, PDF (3/13 Pages) Skyworks Solutions Inc. – 300 kHz - 2.0 GHz Five-Bit Digital Attenuator with Serial-to-Parallel Driver

DATA SHEET • SKY12340-364LF FIVE-BIT DIGITAL ATTENUATOR
Functional Description
The SKY12340-364LF is a five bit digital attenuator comprised of
a GaAs attenuator and a silicon CMOS driver. The attenuation
setting is controlled by a serial-to-parallel interface. Attenuation is
set by a stream of data that is clocked into the shift registers of
the silicon chip by the clock signal.
To set the attenuation state, a latch signal is sent to the
appropriate pin to send the correct bias voltages to the GaAs
attenuator. The silicon chip generates a negative voltage using a
negative voltage generator that requires two external
components: a charge pump capacitor connected between pins
30 (C2) and 31 (C1) and a voltage hold capacitor connected from
pin 28 (VSS) to ground.
More than one attenuator can be cascaded together and the data
may be passed through one device to the other using the
DATA_OUT signal (pin 1). To reset the attenuator to the insertion
loss state, a logic low signal may be sent to the reset pin. DC bias
voltage to the silicon CMOS chip is applied to pin 32 (VDD).
Power-Up/Power-Down Timing
Serial data (SDA) is shifted into the register on the rising edge of
the clock (SCK), least significant bit (LSB) first. The attenuator
changes states on the rising edge of the latch-enable (LE) signal,
according to the most recent five bits of shifted data accepted
since the previous falling edge of the LE signal. Refer to the
timing diagram in Figure 3 and timing parameter specifications in
Table 2.
Power-up sequence is as follows:
0. Connect ground
1. Apply VDD
2. Set all inputs (SCK, SDA, LE)
The power-down sequence is the reverse of above.
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY12340-364LF are
provided in Table 3. Electrical specifications are provided in
Tables 4 and 5.
Typical performance characteristics of the SKY12340-364LF are
illustrated in Figures 4 through 10.
The state of the SKY12340-364LF is determined by the logic
provided in Table 6.
LE
T1
SCK
SDA
Data Feedthrough
T2
T3
T5
Figure 3. Power-Up/Power-Down Timing
Table 2. Power-Up/Power-Down Timing Parameters
Parameter
Symbol
LE setup time
T1
SDA setup time
T2
SDA hold time
T3
LE hold time
T4
Clock frequency
fCLK
Clock period
T5
Minimum
7.5
7.5
5
5
Typical
15
15
10
10
16
1/fCLK
T4
S1594
Maximum
100
Units
ns
ns
ns
ns
MHz
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
201111B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 5, 2010
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