AAT2610_12 Datasheet, PDF (26/31 Pages) Skyworks Solutions Inc. – Seven-Channel PMU for Digital Still Cameras

DATA SHEET
AAT2610
Seven-Channel PMU for Digital Still Cameras
The power dissipation for the synchronous boost channel
in CCM can be calculated by the following equation:
P_Syn-BOOST = I_INBOOST2 ·
R_DS(ON)P
·
V_INBOOST
V ⁺ _OUTBOOST
R_DS(ON)N
·
1
-
V_INBOOST
V_OUTBOOST
Where:
P_Syn-BOOST = Synchronous Boost Channel Power
Dissipation
I_INBOOST = Synchronous Boost Channel Input Current
V_OUTBOOST = Synchronous Boost Channel Output Voltage
V_INBOOST = Synchronous Boost Channel Input Voltage
R_DS(ON)x = Synchronous Boost Channel PMOS or NMOS
Drain-Source On Resistance
The power dissipation for the non-synchronous boost
channel can be calculated by the following equation:
P_Nonsyn-BOOST = I_INBOOST2 ·
R_DS(ON)N ·
1-
V_INBOOST
V_OUTBOOST
Where:
P_Nonsyn-BOOST = Non-Synchronous Boost Channel Power
Dissipation
I_INBOOST = Non-Synchronous Boost Channel Input
Current
V_OUTBOOST = Non-Synchronous Boost Channel Output
Voltage
V_INBOOST = Non-Synchronous Boost Channel Input
Voltage
R_DS(ON)N = Non-Synchronous Boost Channel internal
NMOS Drain-Source On Resistance
The power dissipation for the inverting channel in CCM
can be calculated by the following equation:
P = I · R · _V ^V _{- V Nonsyn-BUCKBOOST}
IN-BUCKBOOST2
DS(ON)P
OUT-BUCKBOOST
IN-BUCKBOOST
OUT-BUCKBOOST
Where:
P_{Nonsyn-BUCKBOOST} = Non-Synchronous Buck/Boost Channel
Power Dissipation
I_IN-BUCKBOOST = Non-Synchronous Buck/Boost Channel
Input Current
V_{OUT-BUCKBOOST} = Non-Synchronous Buck/Boost Channel
Output Voltage
V_IN-BUCKBOOST = Non-Synchronous Buck/Boost Channel
Input Voltage
R_DS(ON)P = Non-Synchronous Buck/Boost Channel inter-
nal PMOS Drain-Source On Resistance
Layout Guidance
When laying out the PC board, the following layout
guideline should be followed to ensure proper operation
of the AAT2610:
1. The exposed pad (EP) must be reliably soldered to
the GND plane for better power dissipation. A PGND
pad below EP is required.
2. The power traces, including the GND trace, the LX
trace and the IN trace should be kept short, direct
and wide to allow large current flow. Each inductor
of the seven channels should be connected to the LX
pins as short as possible. Use several VIA pads when
routing between layers to decrease the conduction
resistance.
3. The input filter capacitor of each channel should con-
nect as closely as possible to IN (Pins 3, 8, 15, 29,
33 and 35) and GND (Pins 5, 6, 26, 27 and 37) to
get good power filtering.
4. Keep the switching node, LX (Pins 4, 7, 25, 29, 34,
36 and 38), away from the sensitive FB node.
5. The feedback trace should be separate from any
power trace and connect as closely as possible to the
load point. Sensing along a high-current load trace
will degrade DC load regulation. The external feed-
back resistors should be placed as closely as possi-
ble to the FB pin (Pin 1, 2, 9, 23, 30, 32 and 40) to
minimize the length of the high impedance feedback
trace.
6. It is recommended to connect the external feedback
resistor divider to the signal ground (Pin 16). The
signal ground and power ground should be con-
nected at a single point to alleviate the power
ground noise affecting the feedback voltage.
7. The resistance of the trace from the load return to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
Figure 4 and 5 show the AAT2610 evaluation board lay-
out with 4 layers.
26
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
202208A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • July 25, 2012