SKY73126-31 Datasheet, PDF (2/14 Pages) Skyworks Solutions Inc. – 161.92 MHz High Performance VCO/Synthesizer

DATA SHEET • SKY73126-31 VCO/SYNTHESIZER
Varactor VCO
/4
Divider
RF_OUT
TCXO_IN
(10 or 32 MHz)
LD
R1
R1
Divider
Vtune
PLL
Loop Filter
SP1
SC1
CPO RF
RF
RF Charge
PFD
Pump
N
Mux
(LD/Test)
N
Divider
3-Wire
Serial
Interface
PS
P/P+1
Prescaler
3.3 V
Voltage
Regulator
RFIN
RFINB
Figure 2. SKY73126-31 Functional Block Diagram
CLK
LE
DATA
VCC (5 V)
S1315
Table 1. SKY73126-31 Signal Descriptions
Pin #
Name
Description
1
VCC
+5 V DC power supply
2
GND
Ground
3
RF_OUT
RF output
4
GND
Ground
5
N/C
No connection
6
GND
Ground
7
N/C
No connection
8
CLK
Serial port clock
Pin #
Name
9
GND
10 DATA
11 LE
12 LD
13 GND
14 TCXO_IN
15 GND
16 GND
Description
Ground
Serial port SPI data input (master out slave in)
Serial port latch enable
Lock detect output
Ground
Frequency reference input
Ground
Ground
Technical Description
The SKY73126-31 is a BiCMOS integer-N synthesizer that offers
high performance, low cost, and low power consumption. The
device also provides programmable charge pump gain.
Serial I/O Control Interface
The SKY73126-31 is programmed through a three-wire serial bus
control interface. The three-wire interface consists of three
signals: CLK (pin 8), LE (pin 11), and the bit serial data line DATA
(pin 10). A serial data input timing diagram is shown in Figure 3.
Timing parameter values are provided in Table 2.
Figure 4 depicts the serial bus, which consists of one 32-bit load
register and four separate 28-bit hold registers. Data is initially
clocked into the load register starting with the Most Significant Bit
(MSB) and ending with the Least Significant Bit (LSB).
The LE signal is used to gate the clock to the load register,
requiring the LE signal to be brought low before the data load.
Data is shifted on the rising edge of CLK. The falling edge of LE
latches the data into the appropriate hold register from the load
register. This programming sequence must be repeated to fill all
four hold registers.
The specific hold register addresses are determined by the wd_0,
wd_1, wd_2, and wd_3 parameters in the load register. These
are the four LSBs (bits [3:0]) as shown in Figure 4. Table 3 lists
the four hold registers and their respective addresses as
determined in the load register.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
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February 24, 2010 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201112C