AAT2783_12 Datasheet, PDF (16/22 Pages) Skyworks Solutions Inc. – Triple-Output PMIC Dual Buck with Low-VIN LDO

DATA SHEET
AAT2783
Triple-Output PMIC: Dual Buck with Low-V_IN LDO
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the capacitance of a 10μF, 6.3V, X5R
ceramic capacitor with 5.0V DC applied is actually about
6μF. The maximum input capacitor RMS current is:
I_RMS = I_O ·
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
V_O
V_IN
· ^⎛⎝1 -
V_O ⎞
V_IN ⎠
=
D · (1 - D) =
0.5² = ¹
2
for V_IN = 2 · V_O
I = _RMS(MAX)
I_O
2
The
term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears in
both
the
input
voltage
ripple and input capacitor RMS current equations and is
a maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle. The input capacitor
provides a low impedance loop for the edges of pulsed
current drawn by the AAT2783. Low ESR/ESL X7R and
X5R ceramic capacitors are ideal for this function. To
minimize stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps the
high frequency content of the input current localized,
minimizing EMI and input voltage ripple. The proper
placement of the input capacitor (C1) can be seen in the
evaluation board layout in the Layout section of this
datasheet (see Figure 2). A laboratory test set-up typi-
cally consists of two long wires running from the bench
power supply to the evaluation board input voltage pins.
The inductance of these wires, along with the low-ESR
ceramic input capacitor, can create a high Q network that
may affect converter performance. This problem often
becomes apparent in the form of excessive ringing in the
output voltage during load transients. Errors in the loop
phase and gain measurements can also result. Since the
inductance of a short PCB trace feeding the input voltage
is significantly lower than the power leads from the
bench power supply, most applications do not exhibit this
problem. In applications where the input power source
lead inductance cannot be reduced to a level that does
not affect the converter performance, a high ESR tanta-
lum or aluminum electrolytic should be placed in parallel
with the low ESR/ESL bypass ceramic capacitor. This
dampens the high Q network and stabilizes the system.
Output Capacitor—Channel 1
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 10μF to
22μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple. The output volt-
age droop due to a load transient is dominated by the
capacitance of the ceramic output capacitor. During a
step increase in load current, the ceramic output capac-
itor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match
the load current demand. The relationship of the output
voltage droop during the three switching cycles to the
output capacitance can be estimated by:
C_OUT
=
3 · ΔI_LOAD
V_DROOP · F_S
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients. The
internal voltage loop compensation also limits the mini-
mum output capacitor value to 10μF. This is due to its
effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
Output Capacitor—Channel 2
The output capacitor limits the output ripple and limits
droop during large load transitions. A 4.7μF to 10μF X5R
or X7R ceramic capacitor typically provides sufficient
bulk capacitance to stabilize the output during large load
transitions and has the ESR and ESL characteristics nec-
essary for low output ripple.
Adjustable Output Resistor Selection
The output voltages on the two AAT2783 buck convert-
ers are programmed with external feedback resistors
R3, R5 and R2, R4. To limit the bias current required for
the external feedback resistor string while maintaining
good noise immunity, the minimum suggested value for
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16
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