AAT2148 Datasheet, PDF (14/18 Pages) Skyworks Solutions Inc. – Low-Noise, Fast Transient 1A Step-Down Converter

DATA SHEET
AAT2148
Low-Noise, Fast Transient 1A Step-Down Converter
V_OUT (V)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.8
1.85
2.0
2.5
3.3
R2 = 59k
R1 (k)
19.6
29.4
39.2
49.9
59.0
68.1
78.7
88.7
118
124
137
187
267
R2 = 221k
R1 ()
75K
113K
150K
187K
221K
261K
301K
332K
442K
464K
523K
715K
1.00M
Table 2: Adjustable Resistor Values For Use With
0.6V Step-Down Converter.
Thermal Calculations
There are three types of losses associated with the
AAT2148 step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of the losses is
given by:
P_TOTAL
=
I_O2
·
(R_DSON(HS)
·
V_O
+ R_DSON(LS)
V_IN
·
[V_IN
-
V_O])
+ (t_sw · F · I_O + I_Q) · V_IN
I_Q is the step-down converter quiescent current. The
term t_sw is used to estimate the full load step-down con-
verter switching losses.
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
P_TOTAL = I_O2 · R_DSON(HS) + I_Q · V_IN
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the _JA for the QFN33-16 pack-
age which is 50°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout
The suggested PCB layout for the AAT2148 is shown in
Figures 2, 3, and 4. The following guidelines should be
used to help ensure a proper layout.
1. The input capacitor (C1) should connect as closely as
possible to V_IN (Pins 9-12) and PGND (Pins 1-3).
2. C2 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX pin should be as
short as possible.
3. The feedback trace or FB pin (Pin 4) should be sepa-
rate from any power trace and connect as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
The external feedback resistors should be placed as
closely as possible to the FB pin (Pin 4) to minimize
the length of the high impedance feedback trace.
4. The resistance of the trace from the load return to
PGND (Pins 1-3) should be kept to a minimum. This
will help to minimize any error in DC regulation due
to differences in the potential of the internal signal
ground and the power ground.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
14
202009A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • May 28, 2012