AAT2120 Datasheet, PDF (13/19 Pages) Advanced Analogic Technologies – 500mA Low Noise Step-Down Converter

Given the total losses, the maximum junction tempera-
ture can be derived from the θ_JA for the STDFN22-8
package which is 50°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout
The suggested PCB layout for the AAT2120 in an
STDFN22-8 package is shown in Figures 2, 3, and 4. The
following guidelines should be used to help ensure a
proper layout.
1. The input capacitor (C1) should connect as closely
as possible to VP (Pin 1), PGND (Pin 8), and GND
(Pin 3)
2. C2 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX pin (Pin 7) should
be as short as possible. Do not make the node small
by using narrow trace. The trace should be kept
wide, direct and short.
DATA SHEET
AAT2120
500mA Low-Noise, Step-Down Converter
3. The feedback pin (Pin 4) should be separate from
any power trace and connect as closely as possible
to the load point. Sensing along a high-current load
trace will degrade DC load regulation. Feedback
resistors should be placed as closely as possible to
the FB pin (Pin 4) to minimize the length of the high
impedance feedback trace. If possible, they should
also be placed away from the LX (switching node)
and inductor to improve noise immunity.
4. The resistance of the trace from the load return to
PGND (Pin 8) and GND (Pin 3) should be kept to a
minimum. This will help to minimize any error in DC
regulation due to differences in the potential of the
internal signal ground and the power ground.
5. A high density, small footprint layout can be achieved
using an inexpensive, miniature, non-shielded, high
DCR inductor.
VIN
C1
4.7μF
U1
1
VP
2 _VIN
8
PGND
L1
LX ^{7 LX}
3
GND
6
EN
4 _FB
N/C ⁵
AAT2120
C2
R1
4.7μF Adj.
+VOUT
C3
(optional)
100pF
GND
Figure 1: AAT2120 Schematic.
R2
59kΩ
GND
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202005A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • May 24, 2012
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