AAT2114A Datasheet, PDF (13/16 Pages) Skyworks Solutions Inc. – 2.5A Low-Noise, Fast Transient 3MHz Step-Down Regulator

DATA SHEET
AAT2114A
2.5A Low-Noise, Fast Transient 3MHz Step-Down Regulator
The typical circuit shown in the AAT2114A evaluation
schematic is intended to be general purpose and suitable
for most applications. In applications where transient
load steps are more severe and the restriction on output
voltage deviation is more stringent, some simple adjust-
ments can be made. The schematic in Figure 1 shows
the configuration for improved transient response in an
application where the output is stepped down to 1.2V.
The adjustments consist of increasing the value of the
feed forward capacitor C₅ to 100pF.
V_OUT (V)
1.0
1.2
1.5
1.8
2.5
3.3
R₄ = 59.0kΩ
R₃ (kΩ)
39.2
59
88.7
118
187
267
R₄ = 221kΩ
R₃ (kΩ)
147
221
332
442
698
1M
Table 2: Feedback Resistors for
Various Output Voltages.
Thermal Calculations
There are three types of losses associated with the
AAT2114A step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of the
power output switching devices. Switching losses are
dominated by the gate charge of the power output switch-
ing devices. At full load, assuming continuous conduction
mode (CCM), a simplified form of the losses is given by:
P_LOSS(RES) = I_O2 · R_DS(ON)H ·
V_O
V_IN
+ R_DS(ON)L ·
V_IN - V_O
V_IN
+ (t_SW · F_SW · I_OUT + I_Q) · V_IN
I_Q is the step-down converter quiescent current. The
term t_SW is the time to charge up the gate capacitor of
the high-side P-channel MOSFET, and used to estimate
the full load step-down converter switching losses.
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the θ_JA for the QFN33-16 pack-
age, which is 43°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout Considerations
The suggested PCB layout for the AAT2114A is shown in
Figures 2 and 3. The following guidelines should be used
to help ensure a proper layout.
1. The input capacitor (C₁) should connect as close as
possible to VP and PGND.
2. C₂, C₃ and L₁ should be connected as close as pos-
sible. The connection of L₁ to the LX pin should be as
short as possible.
3. The feedback trace or FB pin should be separate
from any power trace and connect as close as pos-
sible to the load point. Sensing along a high-current
load trace will degrade DC load regulation.
4. The resistance of the trace from the load return to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
5. Connect unused signal pins to ground to avoid
unwanted noise coupling.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
202004C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 18, 2013
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