AAT2113B Datasheet, PDF (13/22 Pages) Skyworks Solutions Inc. – 3.3MHz, Fast Transient 1.5A Step-Down Converter in an 2mm x 2mm Package

DATA SHEET
AAT2113B
3.3MHz, Fast Transient 1.5A Step-Down Converter in an 2mm x 2mm Package
Input Capacitor
Select a 4.7μF to 10μF X7R or X5R ceramic capacitor for
the input. To estimate the required input capacitor size,
determine the acceptable input ripple level (V_PP) and
solve for C. The calculated value varies with input volt-
age and is a maximum when V_IN is double the output
voltage.
C_IN =
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
⎛ V_PP
⎝ I_O
- ESR^⎞⎠ · F_S
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
=
1
4
for
V_IN
=
2
·
V_O
C_IN(MIN) = _{⎛ VPP}
⎝ I_O
1
- ESR^⎞⎠ · 4 · F_S
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the capacitance of a 10μF, 6.3V, X5R
ceramic capacitor with 3.5V DC applied is actually about
5μF. Some examples of DC bias voltage versus capaci-
tance for different package sizes are shown in Figure 1.
12
0603 Package
10
0805 Package
8
6
4
2
0
0
0.5 1
1.5 2
2.5 3
3.5 4
4.5
DC Bias Voltage (V)
Figure 1: 10μF Capacitor Value vs. DC Bias
Voltage for Different Package Sizes.
The maximum input capacitor RMS current is:
I_RMS = I_O ·
V_{O · 1 -} V_O
V_IN
V_IN
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
V_{O · 1 -} V_{O = D · (1 - D) = 0.52 =} 1
V_IN
V_IN
2
for V_IN = 2 · V_O
I = _RMS(MAX)
I_O
2
The term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears in both the input voltage
ripple and input capacitor RMS current equations and is
a maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle. The input capacitor
provides a low impedance loop for the edges of pulsed
current drawn by the AAT2113B. Low ESR/ESL X7R and
X5R ceramic capacitors are ideal for this function. To
minimize stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps the
high frequency content of the input current localized,
minimizing EMI and input voltage ripple. The proper
placement of the input capacitor (C1) can be seen in the
evaluation board layout in the Layout section of this
datasheet (see Figure 3).
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the eval-
uation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR/ESL bypass ceramic capacitor. This dampens
the high Q network and stabilizes the system.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
202003A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • May 24, 2012
13