SKY72301-22 Datasheet, PDF (12/21 Pages) Skyworks Solutions Inc. – Spur-Free, 1.0 GHz Dual Fractional-N Frequency Synthesizer

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
A3 A2 A1 A0 11 10 9 8 7 6 5 4 3 2 1 0
0 10 1XX
Main Reference Frequency Divider Index
Auxiliary Reference Frequency Divider Index
C1422
Figure 11. Reference Frequency Dividers Register (Write Only)
A3 A2 A1 A0 11 10 9 8 7 6 5 4 3 2 1 0
0 11 0
Main Phase Detector Gain
Main Power Steering/Lock Detect Enable
Auxiliary Phase Detector Gain
Auxiliary Power Steering/Lock Detect Enable
C1423
Figure 12. Phase Detector/Charge Pumps Control Register (Write Only)
The Phase Detector/Charge Pumps Control Register allows control
of the gain for both phase detectors and configuration of the
LD/PSmain and LD/PSaux signals for frequency power steering or
lock detection. As shown in Figure 12, the values to be loaded
are:
• Main Phase Detector Gain = Five-bit value for programmable
main phase detector gain. Range is from 0 to 31 decimal for
31.25 to 1000 µA/2π radian, respectively.
• Main Power Steering Enable = One-bit flag to enable the
frequency power steering circuitry of the main phase detector.
When this bit is cleared, the LD/PSmain pin is configured to be
a lock detect, active-low, open collector pin. When this bit is
set, the LD/PSmain pin is configured to be a frequency power
steering pin and can be used to bypass the external main loop
filter to provide faster frequency acquisition.
• Auxiliary Phase Detector Gain = Five-bit value for
programmable auxiliary phase detector gain. Range is from 0 to
31 decimal for 31.25 to 1000 µA/2π radian, respectively.
• Auxiliary Power Steering Enable = One-bit flag to enable the
frequency power steering circuitry of the auxiliary phase
detector. When this bit is cleared, the LD/PSaux pin is
configured to be a lock detect, active-low, open collector pin.
When this bit is set, the LD/PSaux pin is configured to be a
frequency power steering pin and may be used to bypass the
external auxiliary loop filter to provide faster frequency
acquisition.
The Power Down/Multiplexer Output Select Control Register
allows control of the power-down modes, internal multiplexer
output, and main ∆Σ synthesizer fractionality. As shown in Figure
13, the values to be loaded are:
• Full Power-Down = One-bit flag to power down the SKY72301-
22 except for the reference oscillator and the serial interface.
When this bit is cleared, the SKY72301-22 is powered up. When
this bit is set, the SKY72301-22 is in full power-down mode
excluding the Mux_out signal.
• Main Synthesizer Power-Down = One-bit flag to power down
the main synthesizer. When this bit is cleared, the main
synthesizer is powered up. When this bit is set, the main
synthesizer is in power-down mode.
• Main Synthesizer Mode = One-bit flag to power down the main
synthesizer’s ∆Σ modulator and fractional unit to operate as an
integer-N synthesizer. When this bit is cleared, the main
synthesizer is in a fractional-N mode. When this bit is set, the
main synthesizer is in integer-N mode.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
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May 21, 2007 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200706B