AAT2510 Datasheet, PDF (12/19 Pages) Advanced Analogic Technologies – Dual 400mA, 1MHz Step-Down DC-DC Converter

DATA SHEET
AAT2510
Dual 400mA, 1MHz Step-Down DC/DC Converter
V_OUT (V)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.8
1.85
2.0
2.5
R2, R4 = 59k
R1, R3 (k)
19.6
29.4
39.2
49.9
59.0
68.1
78.7
88.7
118
124
137
187
R2, R4 = 221k
R1, R3 (k)
75
113
150
187
221
261
301
332
442
464
523
715
Table 2: Adjustable Resistor Values
For Use With 0.6V Version.
Thermal Calculations
There are three types of losses associated with the
AAT2510 converter: switching losses, conduction losses,
and quiescent current losses. Conduction losses are
associated with the R_DS(ON) characteristics of the power
output switching devices. Switching losses are dominat-
ed by the gate charge of the power output switching
devices. At full load, assuming continuous conduction
mode (CCM), a simplified form of the dual converter
losses is given by:
P_TOTAL
=
I_O12
·
(R_DSON(HS)
·
V_O1
+ R_DSON(LS)
V_IN
·
[V_IN
-V_O1])
+ ^{IO22 · (RDSON(HS) · VO2 + RDSON(LS) · [VIN -VO2])}
V_IN
+ (t_sw · F · [I_O1 + I_O2] + 2 · I_Q) · V_IN
I_Q is the AAT2510 quiescent current for one channel and
t_sw is used to estimate the full load switching losses.
For the condition where channel one is in dropout at
100% duty cycle, the total device dissipation reduces to:
P_TOTAL = I_O12 · R_DSON(HS)
+ ^{IO22 · (RDSON(HS) · VO2 + RDSON(LS) · [VIN -VO2])}
V_IN
+ (t_sw · F · I_O2 + 2 · I_Q) · V_IN
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the _JA for the TDFN33-12 pack-
age which is 50°C/W.
T_J(MAX) = P_TOTAL • Θ_JA + T_AMB
PCB Layout
The following guidelines should be used to insure a
proper layout.
1. Due to the pin placement of V_IN for both converters,
proper decoupling is not possible with just one input
capacitor. The large input capacitor C3 should con-
nect as closely as possible to V_P and GND, as shown
in Figure 4. The additional input bypass capacitor C8
is necessary for proper high frequency decoupling of
the second converter.
2. The output capacitor and inductor should be con-
nected as closely as possible. The connection of the
inductor to the LX pin should also be as short as pos-
sible.
3. The feedback trace should be separate from any
power trace and connect as closely as possible to the
load point. Sensing along a high-current load trace
will degrade DC load regulation. If external feedback
resistors are used, they should be placed as closely as
possible to the FB pin. This prevents noise from being
coupled into the high impedance feedback node.
4. The resistance of the trace from the load return to
GND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
5. For good thermal coupling, PCB vias are required
from the pad for the TDFN paddle to the ground
plane. The via diameter should be 0.3mm to 0.33mm
and positioned on a 1.2 mm grid.
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202020B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 19, 2013