AAT1185 Datasheet, PDF (11/16 Pages) Skyworks Solutions Inc. – High Voltage Step-Down Controller

The Buck regulator output will remain in a shutdown
state until the internal die temperature falls back below
the 135°C trip point. The combination and interaction
between the short circuit and thermal protection sys-
tems allows the Buck regulator to withstand indefinite
short-circuit conditions without sustaining permanent
damage.
Thermal Calculations
There are three types of losses associated with the
AAT1185 step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of the synchro-
nous step-down converter and LDO losses is given by:
P_TOTAL
=
I_OUT2 · (R_DS(ON)H · V_OUT + R_DS(ON)L · [V_IN - V_OUT])
V_IN
+ (t_SW · F_S · I_OUT + I_Q) · V_IN
I_Q1 is the step-down converter quiescent currents. The
term t_SW is used to estimate the full load step-down con-
verter switching losses.
The power dissipation that relates to the R_DS(ON) occurs in
the external high side and low side MOSFETs. Therefore,
the total package losses for AAT1185 reduce to the fol-
lowing equation:
P_TOTAL = (t_SW · F_S · I_OUT + I_Q1) · V_IN1
Since quiescent current, and switching losses all vary
with input voltage, the total losses should be investi-
gated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the θ_JA for the TSOPJW-14
package, which is 140°C/W.
T_J(MAX) = P_TOTAL · θ_JA + T_AMB
DATA SHEET
AAT1185
High Voltage Step-Down Controller
Layout Considerations
The suggested PCB layout for the AAT1185 is shown in
Figures 5, 6, 7, and 8. The following guidelines should be
used to help ensure a proper layout.
1. The power input capacitors (C3 and C5) should be
connected as closely as possible to the high voltage
input pin (IN) and power ground.
2. C5, L1, Q1, C13, and C14 should be placed as close-
ly as possible to each other to minimize any para-
sitic inductance in the switched current path, which
generates a large voltage spike during the switching
interval. The connection of inductor to switching
node should be as short as possible.
3. The feedback trace or FB pin should be separated
from any power trace and connected as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
4. The resistance of the trace from the load returns to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
5. Connect unused signal pins to ground to avoid
unwanted noise coupling.
6. The critical small signal components, include feed-
back components and compensation components,
should be placed close to the FB1 and COMP1 pins.
The feedback resistors should be located as close as
possible to the FB1 pin with its ground tied straight
to the signal ground plane, which is separated from
the power ground plane.
7. C9 and R3 should be connected as closely as possi-
ble to the RS1 and OS1 pins and placed on the bot-
tom side of the layout to avoid noise coupling from
the inductor.
8. For good thermal coupling, a 4-layer PCB layout is
recommended and PCB vias are required from the
exposed pad (EP) for the MOSFETs paddle to the
middle plane and bottom plane.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
202001A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • May 31, 2012
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