ST7632 Datasheet, PDF (76/96 Pages) Sitronix Technology Co., Ltd. – 4K Color Dot Matrix LCD Controller/Driver

ST7632
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Signal Symbol
tAH8
A0 tAW8
tCYC8
tCCLW
WR
tCCHW
tCCLR
RD
tCCHR
tDS8
tDH8
D0 to D7
tACC8
tOH8
(VDD = 2.8 V , Ta =-30°C ~85°C, die )
Condition
CL = 100 pF
CL = 100 pF
Rating
Min.
Max.
30
—
30
—
470
—
200
—
280
—
80
—
190
—
280
—
30
—
—
140
—
100
Units
ns
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Signal Symbol
tAH8
A0 tAW8
tCYC8
tCCLW
WR
tCCHW
tCCLR
RD
tCCHR
tDS8
tDH8
D0 to D7
tACC8
tOH8
(VDD = 2.0V , Ta =-30°C ~85°C, die )
Condition
Rating
Min.
Max.
Units
30
—
30
—
880
—
340
—
540
—
170
—
ns
360
420
—
30
—
CL = 100 pF
—
240
CL = 100 pF
—
200
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between /CS being “L” and WR and RD being at the “L” level.
Ver 1.7
76/96
2006/08/15