ST7568 Datasheet, PDF (53/73 Pages) Sitronix Technology Co., Ltd. – 68 x 102 Dot Matrix LCD Controller/Driver

ST7568
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Data hold time
READ access time
READ Output disable time
Signal Symbol
tAH6
A0 tAW6
tCYC6
tEWLW
WR
tEWHW
tEWLR
RD
tEWHR
tDS6
tDH6
D0 to D7
tACC6
tOH6
Condition
CL = 100 pF
CL = 100 pF
(VDD = 2.7V , Ta =-30~85°C )
Rating
Units
Min.
Max.
0
—
0
—
400
—
220
—
180
—
220
—
ns
180
—
40
—
15
—
—
140
10
100
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Data hold time
READ access time
READ Output disable time
Signal
Symbol
A0
WR
RD
D0 to D7
tAH6
tAW6
tCYC6
tEWLW
tEWHW
tEWLR
tEWHR
tDS6
tDH6
tACC6
tOH6
Condition
CL = 100 pF
CL = 100 pF
(VDD =1.8V , Ta =-30~85°C )
Rating
Min.
Max.
0
—
0
—
640
—
360
—
280
—
360
—
280
—
80
—
30
—
—
240
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 2.2
53/73
2008/01/04