ST2202A Datasheet, PDF (45/75 Pages) Sitronix Technology Co., Ltd. – 8 BIT Integrated Microcontroller with 256K Bytes ROM

16.4.7 LCD Frame Rate Adjust Register
The LCD frame rate adjust register (LFRA) specifies the
extended time of each scan line. Thus the frame rate slows
down to be the desired value.
Note: LFRA must be a number greater than 4.
The adjusted frame rate for 1- and 4-bit modes can be
found in the following equations
ST2202A
1-bit Mode
LCDCK
Frame Rate =
16 ⋅ (LXMAX + LFRA + 1.5) ⋅ LYMAX
Equation14-1
4-bit Mode
LCDCK
Frame Rate =
4 ⋅ (LXMAX + LFRA + 1.5) ⋅ LYMAX
Equation14-2
16.4.8 LCD Frame Rate Adjust Register
Address Name R/W Bit 7
$049 LFRA W
-
Bit 6
-
Bit 5
FRA[5]
Bit 4
FRA[4]
Bit 3
FRA[3]
Bit 2
FRA[2]
Bit 1
FRA[1]
Bit 0 Default
FRA[0] - -00 0000
Bit 5~0: LFRA[5:0] : Extended time of each scan line
16.4.9 LCD AC Signal Rate Register
The LCD alternating signal rate register (LAC) specifies the time of horizontal lines the alternating signal toggles.
Address Name R/W Bit 7
$04A LAC R/W
-
TABLE 16-8 LCD AC Signal Rate Register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
-
-
AC[4] AC[3] AC[2]
Bit 1
AC[1]
Bit 0 Default
AC[0] - - -0 0000
Bit 2~0:
AC[4:0] : Time of horizontal lines the AC signal toggles
AC[4:0]
00000
00001
00010
00011
:
11101
11110
11111
AC signal
Every frame
Every 3 lines
Every 5 lines
Every 7 lines
:
Every 59 lines
Every 61 lines
Every 63 lines
16.4.10 LCD PWM Contrast Control Register
The ST2202 achieves contrast control function by outputting a PWM signal from BLANK . The duty ratio of PWM signal, also
is the contrast level, is controlled by LPWM[5:0] with 64 steps.
Address Name R/W
$04B LPWM R/W
TABLE 16-9 LCD PWM Contrast Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Default
-
- LPWM[5] LPWM[4] LPWM[3] LPWM[2] LPWM[1] LPWM[0] - - 00 0000
Bit 5~0: LPWM[5~0] : LCD contrast control
LPWM[5:0]
00000
00001
00010
:
11101
11110
11111
Contrast Level
64 (maximum)
63
62
:
3
2
1 (minimum)
Ver 2.5
45/75
9/16/2008