ST2204 Datasheet, PDF (3/24 Pages) Sitronix Technology Co., Ltd. – 8 BIT Integrated Microcontroller with 512K Bytes ROM

ST2204
3. SIGNAL DESCRIPTIONS
Function Group
Power
Ground
System control
Clock
External memory
bus signals
PSG/PWM DAC
Keyboard scan
signal (return line)
GPIO
Chip selects
UART
SPI
Pad No.
18, 55,
94
23, 51,
52, 74
15,
26
50,80
1,81
28
16,
19~22
72, 73
2~4,
85~93,
95~105
75~79,
82~84
53, 54
24~25,
27,29~33
34~41
64~69
48, 49,
70, 71
43~47
TABLE 3-1 Signal Function Groups
Designation
Description
VCC , PVCC
VCC: Power supply for system
PVCC: Power supply for PSGO and PSGOB
GND , PGND
GND: System power ground
PGND: Power ground for PSGO and PSGOB
RESET : Active low system reset signal input
LVR /ICE1:
RESET ,
LVR /ICE1,
ICE2/3,
TEST1/2,
MMD/ CS0
LVR : Low voltage reset signal output, connect this pin to
RESET to make Low Voltage Reset function work.
ICE1: ICE1 function when in ICE mode
TEST1/2, ICE2/3: Leave them open when normal operation
MMD/CS0: Memory modes selection pin
Normal mode: Enable internal ROM.
MMD/ CS0 connects to GND.
Emulation mode: Disable internal ROM.
MMD/ CS0 connects to chip-select pin of external ROM.
One resistor should be added between VCC and this pin.
After reset cycles, MMD/ CS0 changes to be an output, and
outputs signal CS0 .
XMD: High frequency oscillator (OSC) mode selection input
XMD,
XIO,OSCI
OSCXO,OSCXI, ,
Low: Crystal mode. One crystal or resonator should be
connected between OSCI and XIO
High: Resistor oscillator mode. One resistor should be
connected between OSCI and VCC
OSCXI, OSCXO: Connect one 32768Hz crystal between these
two pins when using low frequency oscillator
WR , RD
External memory R/W control signals
A[22:0]
External memory address bus
D[7:0]
External memory data bus
PSGO, PSGOB
PA7~0
PSG outputs. Connect to one buzzer or speaker
I/O port A
PB7~0
CS5 ~ 1/PD4~0,
CS6 /A23/PD5
RXD0/PC7,TXD0/PC6,
RXD1/PD7,TXD1/PD6
DATA_READY /PC5 ,
SS /PC4 , MOSI/PC3 ,
MISO/PC2 , SCK/PC1
I/O port B
I/O port D and chip-select outputs
UART signals and I/Os
SPI signals and I/Os
Ver 0.6
3/24
2008/11/10