ST7576 Datasheet, PDF (19/54 Pages) Sitronix Technology Co., Ltd. – 66 x 102 Dot Matrix LCD Controller/Driver

ST7576
PS2= “L”, PS1= “L”, PS0= “L”: 4-line SPI interface
When the ST7576 is active (CSB=”L”), serial data (D6) and serial clock (D7) inputs are enabled. When CSB is “High”, the
internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication is controlled by the register
selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0
is low. The read feature is not supported in this mode. Serial data on SDA (D6) is latched at the rising edge of serial clock
on SCLK (D7). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column
address pointer will be increased by one automatically after each byte of DDRAM access.
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I T O S ID E
F P C S ID E
S Y S T E M S ID E
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2
3
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7
C = 1 .0 u F
Fig 4 4-line SPI Timing
PS2= “L”, PS1= “L”, PS0= “H”: 3-line SPI interface
When ST7576 is active (CSB=”L”), SDA-out, SDA-in and SCL inputs are enabled. When ST7576 is not active (CSB=”H”),
the internal 8-bit shift register and the 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial
data, an A0 bit is required to indicate the access is data or instruction. The read feature is not supported in this mode
except ID code read feature. Serial data on SDA (D6) is latched at the rising edge of serial clock on SCLK (D7). After the
eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be
increased by one automatically after each byte of DDRAM access.
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. .. . .. .. .. . .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .
. .. .. . .. .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .
.. . .. .
I T O S ID E
F P C S ID E
S Y S T E M S ID E
1
2
3
4
5
6
Fig 5 3-line SPI Timing
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9
C = 1 .0 u F
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Ver 1.0
19/54
2007/01/29