ST7575 Datasheet, PDF (17/51 Pages) Sitronix Technology Co., Ltd. – 66 x 102 Dot Matrix LCD Controller/Driver

ST7575
Test Pins
Pin Name
T0~T8
T11
T12
Type
T
T
T
Description
Do NOT use. Reserved for testing.
Must be floating.
Do NOT use. Reserved for testing.
Must be “L”. Connect to VSS1 for pull-low.
Do NOT use. Reserved for testing.
Must be “L”. Connect to VSS1 for pull-low.
No. of Pins
9
1
1
Recommend ITO Resistance
Pin Name
ITO Resistance
T[0:8], VRS, VDX2O
Floating
VDD1, VDD2, VSS1, VSS2
< 100Ω
V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VMO
A0, RWR, ERD, CSB, D[7:0] ^*1
PS[2:0], OSC ^*2, CP, BR, TMX, TMY, T11, T12
RESB ^*3
< 300Ω
< 1KΩ
< 5KΩ
< 10KΩ
Note:
1. If using 3-Line or 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 500Ω.
2. If using internal clock, OSC is connect to VDD1 and the limitation of ITO resistance will be “No Limitation”.
If using external clock, the ITO resistance of OSC should be kept lower than 300Ω to keep the clock signal quality.
3. To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RESB signal
(add a series resistor or increase ITO resistance). The value is different from modules.
4. The option setting to be “H” should connect to VDD1.
5. The option setting to be “L” should connect to VSS1.
Ver 1.3
17/51
2007/09/12