ST7545T Datasheet, PDF (17/48 Pages) Sitronix Technology Co., Ltd. – 66 x 102 Dot Matrix LCD Controller/Driver

ST7545T
PS0=“H”, PS1=“H”, PS2=“H”: I²C Interface
The I²C interface receives and executes the commands sent via the I²C Interface. It also receives RAM data and sends it to
the RAM. The I²C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are
a Serial Data line (SDA) and a Serial Clock line (SCLK). Both lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes on the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.4.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.5.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.6.
· Transmitter: the device, which sends the data to the bus
· Receiver: the device, which receives the data from the bus
· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
· Slave: the device addressed by a master
· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed
to do so and the message is not corrupted
· Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during the time that master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after receiving each byte. A master receiver must also generate an
acknowledge after receiving each byte which is clocked out by the slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must
signal an end-of-data from the transmitter and stop generating an acknowledge on the last byte which has been clocked
out by the slave. In this moment, the transmitter must leave the data line HIGH and let the master to generate a STOP
condition. Acknowledgement on the I²C Interface is illustrated in Fig.7.
SDA
SCL
Data line stable; ^change
Data valid ^{of data}
allowed
Fig .4 Bit transfer
Ver 1.5
SDA
SCL
S
START condition
P
STOP condition
Fig .5 Definition of START and STOP conditions
17/48
2006/01/20