ST7529 Datasheet, PDF (14/86 Pages) Sitronix Technology Co., Ltd. – 32 Gray Scale Dot Matrix LCD Controller/Driver

ST7529
6.4 MICROPROCESSOR INTERFACE
Name
M0, M1
I/O
Description
M0,M1 must be fixed to VSS. This pin is reserved for internal setting.
I
RST
XCS
IF[3:1]
Reset input pin
I
When RST is “L”, initialization is executed.
Chip select input pins
I Data/instruction I/O is enabled only when XCS is "L". When chip select is non-active, DB0 to
DB15 may be high impedance.
Parallel / Serial data input select input
IF1 IF2 IF3
MPU interface type
H
H
H 80 series 16-bit parallel
H
H
L 80 series 8-bit parallel
I
H
L
L 68 series 16-bit parallel
L
H
H 68 series 8-bit parallel
L
L
H 9-bit serial (3 line)
L
L
L 8-bit serial (4 line)
A0
RW_WR
E_RD
D15 to D0
Register select input pin
I − A0 = "H": DB0 to DB15 or SI are display data
− A0 = "L": DB0 to DB15 or SI are control data
Read / Write execution control pin
MPU type RW_WR
Description
Read / Write control input pin
6800-series
RW
RW = “H” : read
I
RW = “L” : write
Write enable clock input pin
8080-series
/WR
The data on DB0 to DB15 are latched at the
rising edge of the /WR signal.
Read / Write execution control pin
MPU Type
E_RD
Description
Read / Write control input pin
− RW = “H”: When E is “H”, DB0 to DB15 are in an
I
6800-series
E
output status.
− RW = “L”: The data on DB0 to DB15 are latched at
the falling edge of the E signal.
8080-series
Read enable clock input pin
/RD
When /RD is “L”, DB0 to DB15 are in an output status.
They connect to the standard 8-bit or 16-bit MPU bus via the 8/16 –bit bi-directional bus.
When the following interface is selected and the XCS pin is high, the following pins become high
impedance, which should be fixed to VDD or VSS.
I/O _{1. 8-bit parallel: D15-D8 are in the state of high impedance}
2. Serial interface: D15-D0 are in the state of high impedance
SI
I This pin is used to input serial data when the serial interface is selected. (3 line and 4 line)
This pin is used to input serial clock when the serial interface is selected.
SCL
I
The data is latched at the rising edge. (3 line and 4 line)
NOTE:
Microprocessor interface pins should not be floating in any operation mode.
Ver 1.8
14/86
2007/10/25