ISG4042EU-T Datasheet, PDF (8/8 Pages) SIRENZA MICRODEVICES – 5V CATV MODEM RF TUNER AND TRANSMITTER

ISG4042EU-T
PROGRAMMING INFORMATION FOR TX
Serial Interface
The serial interface has an active-low enable (LD_TX) to
bracket the data, with data clocked in MSB first on the ris-
ing edge of CLK. Data is stored in the storage latch on the
rising edge of LD_TX. The serial interface controls the state
of the transmitter. Table 1 and 2 show the register format.
Serial-interface timing is shown in Figure 2. LD_RX must
not be toggled.
A
G
LD_TX
(Pin 6)
CLOCK
(Pin 11)
B
C
DE F
Functional Modes
There are three functional modes controlled through the
serial interface or external pins (Table 2): transmit mode,
transmit disable mode, and software shutdown mode.
Transmit Mode
Transmit mode is the normal active mode. The TXEN pin
must be held high in this mode.
Transmit-Disable Mode
When in transmit-disable mode, the power amplifier is com-
pletely shut off. This mode is activated by taking TXEN low.
This mode is typically used between bursts in TDMA sys-
tems. Transients are controlled by the action of the trans-
former balance.
High Power and Low Noise Modes
The upstream has two transmit modes, high power (HP)
and low noise (LN) Each of these modes is actuated by the
high-order bit D7 of the 8 bit programming word. When D7
is a logic 0, LN mode is enabled.
Each of these modes is characterized by activation of a
distinct output stage. In HP mode, the output stage exhibits
15 dB higher gain than LN mode. The lower gain of the LN
output stage allows for significantly lower output noise and
lower transmit-disable transients.
The full range of gain codes (D6-D0) may be used in either
mode. For DOCSIS applications, HP mode is recom-
mended for output levels at or above +42 dBmV (D7 = 1,
gain code = 87), LN mode when the output level is below
+42 dBmV (D7 = 0, gain code = 115).
DATA
(Pin 12)
D7 D6 D5 D4 D3 D2 D1 D0
A. tSENS
B. tSDAS
C. tSDAH
D. tSCKL
E. tSCKH
F. tSENH
G. tDATAH/tDATAL
Figure 2. Serial-Interface Timing Diagram.
Tx Timing Characteristics
PARAMETER
SYMBOL MIN TYP MAX UNITS
SEN to SCLK Setup Time tSENS 20
ns
SEN to SCLK Hold Time
tSENH 10
ns
SDA to SCLK Setup Time tSDAS 10
ns
SDA to SCLK Hold Time
tSDAH 20
ns
SDA Pulse Width High
tDATAH 50
ns
SDA Pulse Width Low
tDATAL 50
ns
SCLK Pulse Width High
tSLKH 50
ns
SCLK Pulse Width Low
tSLKL 50
ns
Table 1. Serial-Interface Control Word
BIT
MNEMONIC
DESCRIPTION
MSB 7
D7
High-power/low-noise mode select
6
D6
Gain Control, Bit 6
5
D5
Gain Control, Bit 5
4
D4
Gain Control, Bit 4
3
D3
Gain Control, Bit 3
2
D2
Gain Control, Bit 2
1
D1
Gain Control, Bit 1
LSB 0
D0
Gain Control, Bit 0
Table 2. Chip-State Control Bits
TXEN D7
D6 D5 D4 D3 D2
X
X
X
X
X
X
X
0
X
X
X
X
X
X
1
1
X
X
X
X
X
1
0
X
X
X
X
X
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
* Typical gain at +25^OC and VCC = +5 V.
D1 D0 GAIN STATE GAIN
(DECIMAL) (DB)
X
X
X
X
X
X
X
X
0
0
48
-26
0
0
80
-10
1
1
115
8
1
1
87
9
1
0
110
20
0
1
125
28
STATES
Shutdown Mode
Transmit-Disable Mode
Transmit Mode-Enable Mode, High Power
Transmit Mode-Enable Mode, Low Noise
303 S. Technology Court, Broomfield, CO 80021
303-327-3030
8
www.sirenza.com
REV. A
4/1/2005