SDM-09120_1 Datasheet, PDF (2/5 Pages) SIRENZA MICRODEVICES – 925-960 MHz Class AB 130W Power Amplifier Module

SDM-09120 925-960 MHz 130W Power Amp Module
Pin Description
Pin # Function
Description
1
2,4,7,9
V_GS1
Ground
LDMOS FET Q1 and Q2 gate bias. V_GSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4
Module Topside ground.
3
RF Input Internally DC blocked
5
V_GS2
LDMOS FET Q3 and Q4 gate bias. V_GSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4
6
V_D2
LDMOS FET Q3 and Q4 drain bias. See Note 1.
8
RF Output Internally DC blocked
10
Flange
V_D1
Ground
LDMOS FET Q1 and Q2 drain bias. See Note 1.
Baseplate provides electrical ground and a thermal transfer path for the device. Proper mounting assures
optimal performance and the highest reliability. See Sirenza applications note AN-054 Detailed Installation Instructions for
Power Modules.
Simplified Device Schematic
Q1
1 ^{+3V DC to +6 V DC}
10 ^{+28V DC}
2
Q2
o
180
3
Balun
Q3
0^o
4
Q4
5 ^{+3V DC to +6 V DC}
9
0^o
Balun
8
o
180
7
+28V DC
6
Absolute Maximum Ratings
Parameters
Value
Unit
Drain Voltage (V_DD)
RF Input Power
35
V
+43
dBm
Load Impedance for Continuous Operation
Without Damage
5:1
VSWR
Control (Gate) Voltage, VDD = 0 VDC
15
V
Output Device Channel Temperature
+200
ºC
Operating Temperature Range
-20 to
+90
ºC
Storage Temperature Range
-40 to
+100
ºC
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
Note 1:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the V_D leads to
accommodate modulated signals.
Note 2:
Gate voltage must be applied to V_GS leads simultaneously with
or after application of drain voltage to prevent potentially
destructive oscillations. Bias voltages should never be applied
to a module unless it is properly terminated on both input and
output.
Note 3:
The required V_GS corresponding to a specific I_DQ will vary from
module to module and may differ between V_GS1 and V_GS2 on
the same module by as much as ±0.10 volts due to the normal
die-to-die variation in threshold voltage for LDMOS transistors.
Note 4:
The threshold voltage (V_GSTH) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature Compensation.
Note 5:
This module was designed to have it's leads hand
soldered to an adjacent PCB. The maximum soldering iron tip
temperature should not exceed 700° F, and the soldering iron
tip should not be in direct contact with the lead for longer than
10 seconds. Refer to app note AN054 (www.sirenza.com) for
further installation instructions.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-103478 Rev G