XD010-12S-D4F Datasheet, PDF (1/6 Pages) SIRENZA MICRODEVICES – 869-894 MHz Class AB 15W Power Amplifier Module

Product Description
Sirenza Microdevices’ XD010-12S-D4F 15W power module is a robust 2-
stage Class A/AB amplifier module for use in the driver stages of cellular
base station power amplifiers. The power transistors are fabricated using
Sirenza's latest, high performance LDMOS process. It is a drop-in, no-tune,
solution for high power applications requiring high efficiency, excellent linear-
ity, and unit-to-unit repeatability. This unit operates from a single voltage sup-
ply and has internal temperature compensation of the bias voltage to ensure
stable performance over the full temperature range. It is internally matched
to 50 ohms.
Functional Block Diagram
Stage 1
Stage 2
Bias
Network
1
2
RF in
VD1
Temperature
Compensation
3
4
VD2
RF out
XD010-12S-D4F
869-894 MHz Class AB
15W Power Amplifier Module
Product Features
• 50 W RF impedance
• 15W Output P_1dB
• Single Supply Operation : Nominally 28V
• High Gain: 32 dB at 880 MHz
• Robust 8000V ESD (HBM), Class 3B
• XeMOS II LDMOS FETS
• Temperature Compensation
Applications
• Base Station PA driver
• Repeater
• CDMA / WCDMA
• GSM / EDGE
Case Flange = Ground
Key Specifications
Symbol
Parameter
Unit
Frequency
Frequency of Operation
MHz
P_1dB
Output Power at 1dB Compression, 880MHz
W
Gain
Gain at 1W Output Power, 880MHz
dB
Gain Flatness
Peak to Peak Gain Variation, 869 - 894MHz
dB
IRL
Input Return Loss 1W Output Power, 869 - 894MHz
dB
Drain Efficiency at 12W CW, 880MHz
%
Efficiency
Drain Efficiency at 2W CDMA (Single Carrier IS-95)
%
Drain Efficiency at 1W CDMA (Single Carrier IS-95)
%
ACPR at 2W CDMA (Single Carrier IS-95, 9 Ch Fwd, Off-
set=750KHz, ACPR Integrated Bandwidth), 880MHz
dB
Linearity
ALT-1 at 2W CDMA (Single Carrier IS-95, 9 Ch Fwd,
Offset=1980KHz, ACPR Integrated Bandwidth), 880MHz
dB
3^rd Order IMD at 12W PEP (Two Tone), 880MHz
dBc
3^rd Order IMD at 1W PEP (Two Tone), 880MHz
dBc
Delay
Signal Delay from Pin 1 to Pin 4
nS
Phase Linearity
Deviation from Linear Phase (Peak to Peak)
Deg
R_{TH, j-l}
R_{TH, j-2}
Thermal Resistance Stage 1 (Junction to Case)
Thermal Resistance Stage 2 (Junction to Case)
ºC/W
ºC/W
Test Conditions Z_in = Z_out = 50Ω, V_D = 28.0V, I_DQ1 = 230 mA, I_DQ2 =150mA, T_Flange = 25ºC
Min.
869
12
30
-
14
27
-
-
-
-
-
-
-
-
-
-
Typ.
-
15
32
0.2
17
33
12
7
-51
-70
-36
-45
2.5
0.5
11
4
Max.
894
-
-
1.0
-
-
-
-
-
-
-32
-
-
-
-
-
1625-1675The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and
all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
1
EDS-102934 Rev C