SPF-3043 Datasheet, PDF (1/4 Pages) Stanford Microdevices – Low Noise pHEMT GaAs FET

Product Description
Sirenza Microdevices’ SPF-3043 is a high performance
0.25µm pHEMT Gallium Arsenide FET. This 300µm device is
ideally biased at 3V,20mA for lowest noise performance and
battery powered requirements. At 5V,40mA the device can
deliver OIP3 of 32dBm. It provides ideal performance as a
driver stage in many commercial and industrial LNA
applications.
Preliminary
SPF-3043
Low Noise pHEMT GaAs FET
Pending Obsolescence
Last Time Buy Date: Dec. 19, 2003
Typical Gain Performance
35
3V,20mA
5V,40mA
30
25
20
Gmax
Product Features
• DC-10 GHz Operation
• 0.5 dB NF_MIN @ 2 GHz
• 22 dB G_MAX @ 2 GHz
• +32 dBm OIP3 (5V,40mA)
• +20 dBm P1dB (5V,40mA)
• Low Current, Low Cost
• Apps circuits available for key bands
15
Gain
10
Applications
• Analog and Digital Wireless Systems
5
• 3G, Cellular, PCS
0
2
4
6
8
10
• Fixed Wireless, Pager Systems
Frequency (GHz)
• Driver Stage for Low Power Applications
Symbol Device Characteristics
Test Conditions
V_DS=5V, I_DQ=40mA, 25ºC
(unless otherwise noted)
Test
Frequency
Units
Min.
Typ.
Max.
G_MAX Maximum Available Gain
Z_S=Z_S*, Z_L=Z_L*
0.9 GHz
1.9 GHz
dB
26.5
23.4
NF_MIN Minimum Noise Figure
Z_S=Γ_OPT , Z_L=Z_L*
0.9 GHz
1.9 GHz
dB
0.32
0.54
S₂₁
Insertion Gain ^[1]
NF
Noise Figure ^[2]
Z_S=Z_L= 50Ω
LNA Application Circuit Board
0.9 GHz
1.9 GHz
dB
18.5 20.0 21.5
dB
1.05 1.40
Gain Gain ^[2]
LNA Application Circuit Board
1.9 GHz
dB
14.0 15.3
OIP₃
P_1dB
V_P
I_DSS
g_m
BV_GSO
BV_GDO
Rth
Output Third Order Intercept Point ^[2] LNA Application Circuit Board
Output 1dB Compression Point ^[2] LNA Application Circuit Board
Pinchoff Voltage ^[1]
Saturated Drain Current ^[1]
Transconductance ^[1]
Gate-Source Breakdown Voltage ^[1]
Gate-Drain Breakdown Voltage ^[1]
Thermal Resistance
V_DS= 2V, I_DS= 0.1 mA
V_DS= 2V, V_GS= 0 V
V_DS= 2V, V_GS= 0 V
I_GS= 0.03 mA, drain open
I_GD= 0.03 mA, source open
junction-to-lead
1.9 GHz
dBm 26.0 28.5
1.9 GHz
dBm 15.0 17.0
V
-1.1 -0.8 -0.5
mA
30
60
120
mS
90
150
V
-10
-8
V
-10
-8
ºC/W
150
V_DS Operating Voltage
drain-source
V
5.5
I_DS
Operating Current
drain-source
mA
55
[1] 100% tested - DC parameters tested on-wafer, insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test.
[2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from 500 devices across 5 wafers, 3 wafer lots. The
test fixture is an engineering application circuit board (parts are pressed down on the circuit board). The application circuit represents a trade-off between the optimal noise
match and input return loss.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are
subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not
authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems.
Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
1
EDS-101772 Rev D