SP6120HV Datasheet, PDF(9/22 Page) Sipex Corporation – High Voltage, Synchronous ,Buck Controller Ideal for 2A to 20A, High Performance, DC-DC Power Converters

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SP6120HV Datasheet, PDF (9/22 Pages) Sipex Corporation – High Voltage, Synchronous ,Buck Controller Ideal for 2A to 20A, High Performance, DC-DC Power Converters

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General Overview: continued

if the conduction current reaches zero and the

Driver Logic has made an attempt to turn the

lower driver on and the Programming Logic is

set for discontinuous mode. Lastly, the 4â¦ driv-

ers have internal gate non-overlap circuitry and

are designed to drive MOSFETs associated with

converter designs in the 5A to 10A range. Typi-

cally the high side driver is referenced to the

SWN pin; further improving the efficiency and

performance of the converter.

ENABLE

Low quiescent mode or âSleep Modeâ is initi-

ated by pulling the ENABLE pin below 650mV.

The ENABLE pin has an internal 4ÂµA pull-up

current and does not require any external inter-

face for normal operation. If the ENABLE pin is

driven from a voltage source, the voltage must

be above 1.45V in order to guarantee proper

âawakeâ operation. Assuming that VCC is above

2.85V, the SP6120HV transitions from âSleep

Modeâ to âAwake Modeâ in about 20Âµs to 30Âµs

and from âAwake Modeâ to âSleep Modeâ in a

few microseconds. SP6120HV quiescent cur-

rent in sleep mode is 20ÂµA maximum. During

Sleep Mode, the high side and low side MOSFETs

are turned off and the COMP and SS pins are

held low.

Bootstrap Circuit

When SP6120HV is programmed to drive a

high side N channel MOSFET, a bootstrap cir-

cuit is required to generate a voltage higher than

VIN to fully enhance the top MOSFET. A typical

bootstrap only requires a capacitor and diode

shown as CBST and DBST in the application

circuit on the front page. When the bottom

MOSFET QB is turned on, DBST is forward

biased and charges the CBST close to VIN. When

the top MOSFET turn on, the switch node swings

to the VIN voltage. Now the voltage at the BST

pin is 2*VIN and DBST is reverse biased. The

BST pin voltage powers the high side MOSFET

driver, and thus the GH output goes up to 2*VIN

to provide a VDS equal to VIN.

Under certain conditions, the bottom MOSFET

may not turn on long enough to replenish CBST

voltage. Therefore, when the top MOSFET turns

on, the BST pin may not be high enough to fully

enhance the switch. To prevent this operation,

SP6120HV monitors the BST pin voltage in

reference to the VCC voltage. When the BST pin

voltage is less than VBST OK threshold, the

controller forces the GL to turn on for MINI-

MUM GL ON at the end of the switching cycle.

This provides enough time to recharge the CBST

and ensures the proper operation of the boot-

strap circuit.

UVLO

Assuming that the ENABLE pin is either pulled

high or floating, the voltage on the VCC pin then

determines operation of the SP6120HV. As VCC

rises, the UVLO block monitors VCC and keeps

the high side and low side MOSFETs off and the

COMP and SS pins low until VCC reaches 2.85V.

If no faults are present, the SP6120HV will

initiate a soft start when VCC exceeds 2.85V.

Hysteresis (about 100mV) in the UVLO com-

parator provides noise immunity at start-up.

Soft Start

(see figures on next page)

Soft start is required on step-down controllers to

prevent excess inrush current through the power

train during start-up. Typically this is managed

by sourcing a controlled current into a program-

ming capacitor (on the SS pin) and then using the

voltage across this capacitor to slowly ramp up

either the error amp reference or the error amp

output (COMP). The control loop creates nar-

row width driver pulses while the output voltage

is low and allows these pulses to increase to their

steady-state duty cycle as the output voltage

increases to its regulated value. As a result of

controlling the inductor volt*second product

during start-up, inrush current is also controlled.

The presence of the output capacitor creates

extra current draw during start-up. Simply stated,

dVOUT/dt requires an average sustained current

in the output capacitor and this current must be

considered while calculating peak inrush current

and over current thresholds. Since the SP6120HV

ramps up the error amp reference voltage, an

expression for the output capacitor current can

be written as:

ICOUT = (COUT/CSS) * (VOUT/1.25) * 50ÂµA

Date: 5/25/04

SP6120HV Low Voltage, Synchronous Buck Controller

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