SP3203E_05 Datasheet, PDF (9/16 Pages) Sipex Corporation – 3V RS-232 Serial Transceiver with Logic Selector and15kV ESD Protection

SHUTDOWN
DEVICE: SP3203E
T_XOUT
R_XOUT
0
High-Z
High-Z
1
Active
Active
Charge
Pump
Inactive
Active
Table 1. SHUTDOWN Truth Table.
(Note: When device in shutdown, the SP3203E's charge pump is turned off
and V+ decays to V_CC. V- is pulled to ground and the transmitter outputs
are disabled as High Impendance).
consists of a regulated dual charge pump that
provides output voltages of 5.5V regardless of
the input voltage (V_CC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a of 5.5V, the charge
pump is enabled. If the output voltages exceed
a of 5.5V, the charge pump is disabled. This
oscillator controls the four phases of the voltage
shifting (Figure 12). A description of each phase
follows.
V_SS Charge Storage-Phase 1(Figure 13)
During this phase of the clock cycle, the positive
side of capacitors C₁ and C₂ are initially charged
to V_CC. C_l+ is then switched to GND and the
charge in C_1– is transferred to C_2–. Since C₂₊ is
connected to V_CC, the voltage potential across
capacitor C₂ is now 2 times V_CC.
+3V to +5V
+
C5 0.1µF
+
C1 0.1µF
+
C2 0.1µF
1 _C1+
3 C1-
4 C2+
5 C2-
19
VCC
SP3203E
V+ ²
V- ⁶
TTL/CMOS
INPUTS
T₁IN
T_XIN
T₁OUT
T_XOUT
+
C3 0.1µF
C4 0.1µF
+
TTL/CMOS
OUTPUTS
R₁OUT
R₁IN
5KΩ
R_XOUT
R_XIN
5KΩ
VCC
20
SHUTDOWN
1000pF
1000pF
GND
18
12
VL
+3V to +5.5V
Figure 9. Loopback Test Circuit for RS-232 Driver Data
Transmission Rates
V_SS Transfer-Phase 2 (Figure 14)
Phase two of the clock connects the negative
terminal of C₂ to the V_SS storage capacitor and
the positive terminal of C₂ to GND. This
transfers a negative generated voltage to C₃.
This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage
to C₃, the positive side of capacitor C₁ is
switched to V_CC and the negative side is
connected to GND.
V_DD Charge Storage-Phase 3 (Figure 15)
The third phase of the clock is identical to the
first phase — the charge transferred in C₁ pro-
T1 IN 1
[
T
]
T
T1 OUT 2
T
T
R1 OUT 3
Ch1 5.00V Ch2 5.00V M 5.00µs Ch1
0V
Ch3 5.00V
[
T
]
T
T1 IN 1
T1 OUT 2
T
T
R1 OUT 3
Ch1 5.00V Ch2 5.00V M 2.50µs Ch1
0V
Ch3 5.00V
Figure 10. Loopback Test Circuit Result at 120Kbps
(All Drivers Fully Loaded)
Figure 11. Loopback Test Circuit result at 250Kbps
(All Drivers Fully Loaded)
Date: 03/01/05
SP3203E, 3V RS232 Serial Transceiver with Logic Selector and 15kV ESD
© Copyright 2005 Sipex Corporation
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