SP691A_05 Datasheet, PDF (8/24 Pages) Sipex Corporation – Low Power Microprocessor Supervisory with Battery Switch-Over

PINOUT
TOP VIEW
VBATT 1
VOUT 2
Vcc 3
GND 4
BATT ON 5
LOWLINE 6
OSCIN ⁷
OSCSEL 8
Corporation
DIP/SO
16 RESET
15 RESET
14 WDO
13 CEIN
12 CEOUT
11 WDI
10 _PFO
9 PFI
PIN ASSIGNMENTS
Pin 1 — V_BATT — Battery-Backup Input. Con-
nect to the external battery supply or super-
charging capacitor and charging circuit. If a
backup battery is not provided, connect this
pin to ground.
Pin 2 —V — Output Supply Voltage. V
OUT
OUT
connects to V when V is greater than
CC
CC
V_BATT and V_CC is above the reset threshold.
When V falls below V and V is
CC
BATT
CC
below the reset threshold, V_OUT connects to
V.
BATT
Connect
a
0.1µF
capacitor
from
V
OUT
to GND.
Pin 3 — V_CC — +5V Input Supply Voltage.
Pin 4 — GND — Ground reference for all
signals.
Pin 5 — BATT ON — Battery On Output. Goes
high when V switches to V . Goes low
OUT
BATT
when V switches to V . Connect the
OUT
CC
base of a PNP through a current-limiting
resistor to BATT ON for V current
OUT
requirements greater than 250mA.
Pin 6 — LOWLINE — Low Line Output. This
output pin goes LOW when V_CC falls below
the reset threshold voltage. This output pin
returns to its HIGH output as soon as V_CC
rises above the reset threshold voltage.
Pin 7 — OSC_IN — External Oscillator Input.
When OSC_SEL is unconnected or driven
HIGH,
a
10µA
pull-up
connects
from
V
OUT
to this input pin, the internal oscillator sets
the reset and watchdog timeout periods, and
this input pin selects between fast and slow
watchdog timeout periods. When OSC_SEL is
driven LOW, the reset and watchdog timeout
periods may be set either by a capacitor from
this input pin to ground or by an external
clock at this pin (refer to Figure 21).
Pin 8 — OSC_SEL — Oscillator Select. When
OSC is unconnected or driven HIGH, the
SEL
internal oscillator sets the reset delay and
watchdog timeout period. When OSC is
SEL
driven LOW, the external oscillator input
pin, OSC_IN, is enabled (refer to Table 1).
This input pin has a 10µA internal pull-up.
Pin 9 — PFI — Power-Fail Input. This is the
noninverting input to the power-fail
comparator. When PFI is less than 1.25V,
PFO goes low. Connect PFI to GND or
V_OUT when not used.
Pin 10 — PFO — Power-Fail Output. This is
the output of the power-fail comparator.
PFO goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and
has no effect on any other internal circuitry.
Pin 11 — WDI — Watchdog Input. This is a
three-level input pin. If WDI remains either
HIGH or LOW for longer than the watchdog
timeout period, WDO goes LOW and RESET
is asserted for the reset timeout period. WDO
remains LOW until the next transition at this
input pin. Leaving this input pin unconnected
disables the watchdog function. This input
pin connects to an internal voltage divider
between V and ground, which sets it to
OUT
mid-supply when left unconnected.
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
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