SP3281EB Datasheet, PDF (8/15 Pages) Sipex Corporation – Intelligent +2.35V to +5.5V RS-232 Transceivers

— V_SS charge storage — During this phase of the
Ct.coSl₂^{oGiacnrkNceecDinCyica}₂tlin₊^{eadi,lslttychhoceehnpcanhoreagscirettgiedvedteoitnosViCVd}_C1^e_CC–.o_CiC,fstclth⁺_{raeaipsnvatsohcfleiettnraorgrseswedCpittoo}¹ctahCenen₂^dd_–-
tial across capacitor C₂ is now 2 times V_CC.
Phase 2 (Figure 12)
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂ to
GND. This transfers a negative generated voltage
to C₃. This generated voltage is
regulated to a minimum voltage of -5.5V (V_CC >
3.3V) and -4.0V (V_CC < 3.1V).
Simultaneous with the transfer of the voltage to C₃,
the positive side of capacitor C₁ is switched to V_CC
and the negative side is connected to GND.
Phase 3 (Figure 13)
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –V_CC in the negative
terminal of C₁, which is
of capacitor C₂. Since
applied to the negative side
C₂₊ is at V_CC, the voltage
potential across C₂ is 2 times V_CC.
Phase 4 (Figure 14)
— V_DD transfer — The fourth phase of the clock
connects the negative terminal of C₂ to GND, and
transfers this positive generated voltage across C₂
to C₄, the V_DD storage capacitor. This voltage is
regulated to +5.5V (V_CC>3.3V) and
+4.0V(V_CC<3.1V). At this voltage, the internal
oscillator is disabled. Simultaneous with the trans-
fer of the voltage to C₄, the positive side of capaci-
tor C₁ is switched to V_CC and the negative side is
connected to GND, allowing the charge pump
cycle to begin again. The charge pump cycle will
continue as long as the operational conditions for
theinternal oscillator are present.
Since both V⁺ and V^– are separately generated
VCC
from V_CC, in a no–load condition V⁺ and V^– will be
symmetrical. Older charge pump approaches that
generate V^– from V⁺ will show a decrease in the
magnitude of V^– compared to V⁺ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 500kHz. The external capacitors should
be 0.22µF with a 16V working voltage rating for
a V_CC input range of +2.35V to +5.5V.
Charge Pump Capacitor Selection
The charge pump capacitors C1-C4 and bypass
C5 can be of any type including ceramic. If
polarized capacitors are used, refer to figure 3
application diagram for proper orientation. The
following chart illustrates the minimum capaci-
tor valve for a given input voltage range.
V_CC (V)
3.0 to 3.6
4.5 to 5.5
2.35 to 5.5
C1 and C5 (µF)
0.1
0.047
0.22
C2,C3,C4 (µF)
0.1
0.33
0.22
+
C1 _-
-VCC
Figure 11. Charge Pump — Phase 1
+VCC
C2 ⁺
-
-VCC
C4
+ - _{VDD Storage Capacitor}
-+
VSS Storage Capacitor
C3
Rev. 6/19/03
SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers
8
© Copyright 2003 Sipex Corporation