SP3249E Datasheet, PDF (8/14 Pages) Sipex Corporation – Intelligent +3.0V to +5.5V RS-232 Transceivers

— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –V_CC in the negative
terminal of C₁, which
side of capacitor C₂.
is applied to the
Since C₂₊ is at
negative
V_CC, the
voltage potential across C₂ is 2 times V_CC.
Phase 4 (Figure 15)
— V_DD transfer — The fourth phase of the clock
connects the negative terminal of C₂ to GND,
and transfers this positive generated voltage
across C₂ to C₄, the V_DD storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the
positive side of capacitor C₁ is switched to V_CC
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Since both V⁺ and V^– are separately generated
from V_CC, in a no–load condition V⁺ and V^– will
be symmetrical. Older charge pump approaches
that generate V^– from V⁺ will show a decrease in
the magnitude of V^– compared to V⁺ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 500kHz. The external capacitors can
be as low as 0.1µF with a 16V breakdown
voltage rating.
Figure 10. Charge Pump — Phase 1
V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
V_CC = +5V
+
C_{1 –}
Figure 11. Charge Pump — Phase 2
+
C_{2 –}
–10V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
a) C2+
1
2
2
[
T
T
]
+6V
0V
0V
b) C2-
T
-6V
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V
Figure 12. Charge Pump Waveforms
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
8
© Copyright 2002 Sipex Corporation