SP6132EB Datasheet, PDF (7/9 Pages) Sipex Corporation – Evaluation Board Manual

f. Select the ratio of Rz2 / R1 gain for the desired gain bandwidth
Rz2 = (R1) (Vramp_pp / Vin) (fco / fp_LC)
g. Calculate Cz2 by placing the zero at ½ of the output filter pole frequency
Cz2 = 1 / π (Rz2) (fp_LC)
h. Calculate Cp1 by placing the first pole at ESR zero frequency
Cp1 = 1 / 2π (Rz2) (fz_ESR)
i. Calculate Rz3 by setting the second pole at ½ of the switching frequency and the
second zero at the output filter double pole frequency
Rz3 = 2 (R1) (fp_LC) / fs
j. Calculate Cz3 from Rz3 component value above
Cz3 = 1 / π (Rz3) (fs)
k. Choose 100pF ≤ Cf1 ≤ 220pF to stabilize the SP6132CU internal Error Amplify
As a particular example, consider for the following SP6132EB with a type III Voltage
Loop Compensation component selections:
Vin = 5 to 12V
Vout = 3.30V @ 0 to 10A load
Select L = 2.7uH => yield ≈ 20% of maximum 10A output current ripple.
Select Cout = 2x47uF Ceramic capacitors (Resr ≈ 2mΩ)
fs = 300khz SP6132CU internal Oscillator Frequency
Vramp_pp = 1.0V SP6132CU internal Ramp Peak to Peak Amplitude
Step by step design procedures:
a. fco = 300khz / 5 = 60khz
b. fp_LC = 1 / 2π [(2.7uH)(2)(47uF)]^1/2 ≅ 10khz
c. fz_ESR = 1 / 2π (2mΩ)(2)(47uF) ≈ 850khz
d. R1 = 68.1kΩ, 1%
e. R2 = 68.1kΩ / [(3.30V / 0.80V) – 1] ≅ 21.5kΩ, 1%
f. Rz2 = 68.1kΩ (1.0V / 12V) (60khz / 10khz) ≈ 40.2kΩ, 1%
g. Cz2 = 1 / π (40.2kΩ) (10khz) ≈ 820pF, COG
h. Cp1 = 1 / 2π (40.2kΩ) (850khz) ≈ 5pF => Select Cp1 = 56pF for noise filtering
i. Rz3 = 2 (68.1kΩ) (10khz) / 300khz ≈ 4.64kΩ, 1%
j. Cz3 = 1 / π (4.64kΩ) (300khz) ≅ 220pF, COG
k. Cf1 = 100pF to stabilize SP6132CU internal Error Amplify
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