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SP503 Datasheet, PDF (7/29 Pages) Sipex Corporation – Multiprotocol Transceiver | |||
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Pin 71 â RD(b) â Receive Data; analog input;
non-inverted; source for RxD.
Pin 76 â SCT(a) â Serial Clock Transmit;
analog input, inverted; source for SCT.
Pin 77 â SCT(b) â Serial Clock Transmit:
analog input, nonâinverted; source for SCT
Pin 79 â SCT â Serial Clock Transmit; TTL
output; sources from SCT(a) and SCT(b) inputs.
CONTROL LINE GROUP
Pin 13 â DTR â Data Terminal Ready; TTL
input; source for TR(a) and TR(b) outputs.
Pin 16 â RTS â Ready To Send; TTL input;
source for RS(a) and RS(b) outputs.
Pin 17 â RL â Remote Loopback; TTL input;
source for RL(a) and RL(b) outputs.
Pin 19 â DCDâ Data Carrier Detect; TTL
output; sourced from RR(a) and RR(b) inputs.
Pin 21 â RI â Ring In; TTL output; sourced
from IC(a) and IC(b) inputs.
Pin 24 â LL â Local Loopback; TTL input;
source for LL(a) and LL(b) outputs.
Pin 35 â RR(a)â Receiver Ready; analog
input, inverted; source for DCD.
Pin 36 â RR(b)â Receiver Ready; analog
input, non-inverted; source for DCD.
Pin 39 â IC(a)â Incoming Call; analog input,
inverted; source for RI.
Pin 40 â IC(b)â Incoming Call; analog input,
non-inverted; source for RI.
Pin 45 â RL(b) â Remote Loopback; analog
output, non-inverted; sourced from RL.
Pin 47 â RL(a) â Remote Loopback; analog
output inverted; sourced from RL.
Pin 49â LL(b) â Local Loopback; analog
output, non-inverted; sourced from LL.
Pin 51 â LL(a) â Local Loopback; analog
output, inverted; sourced from LL.
Pin 52 â RS(b) â Ready To Send; analog
output, non-inverted; sourced from RTS.
Pin 54 â RS(a) â Ready To Send; analog
output, inverted; sourced from RTS.
Pin 56 â TR(b) â Terminal Ready; analog
output, non-inverted; sourced from DTR.
Pin 58 â TR(a) â Terminal Ready; analog
output, inverted; sourced from DTR.
Pin 66 â CS(a)â Clear To Send; analog input,
inverted; source for CTS.
Pin 67 â CS(b)â Clear To Send; analog input,
non-inverted; source for CTS.
Pin 68 â DM(a)â Data Mode; analog input,
inverted; source for DSR.
Pin 69 â DM(b)â Data Mode; analog input,
non-inverted; source for DSR
Pin 78 â DSRâ Data Set Ready; TTL output;
sourced from DM(a), DM(b) inputs.
Pin 80 â CTSâ Clear To Send; TTL output;
sourced from CS(a) and CS(b) inputs.
CONTROL REGISTERS
Pins 2â5 â RDEC0 â RDEC3 â Receiver
decode register; configures receiver modes; TTL
inputs.
Pin 6 â TTEN â Enables TT driver, active
low; TTL input.
Pin 7 â SCTEN â Enables SCT receiver;
active high; TTL input.
Pins 12â9 â TDEC0 â TDEC3 â Transmitter
decode register; configures transmitter modes;
TTL inputs.
Pin 23 â STEN â Enables ST driver; active
low; TTL input.
POWER SUPPLIES
Pins 8, 25, 33, 41, 48, 55, 62, 73, 74 â VCC â
+5V input.
Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 â
GND â Ground.
Pin 27 â VDD +10V Charge Pump Capacitor â
Connects from VDD to VCC. Suggested capaci-
tor size is 22µF, 16V.
Date: 7/29/04
SP503 Multiprotocol Transceiver
7
© Copyright 2004 Sipex Corporation
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