SP385E-1 Datasheet, PDF (6/11 Pages) Sipex Corporation – True +3V or +5V RS-232 Line Driver/Receiver

CHARGE PUMP
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 10V
power supplies. There is a free–running
oscillator that controls the four phases of the
voltage shifting. A description of each phase
follows.
Phase 1
— V_SS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C₁ and C₂ are initially charged to +5V. C_l+ is
then switched to ground and the charge in C_1–
is transferred to C_2–. Since C₂₊ is connected to
+5V, the voltage potential across capacitor C₂
is now 10V.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the
V_SS storage capacitor and the positive
terminal of C₂ to ground, and transfers the
generated –l0V to C₃. Simultaneously, the
positive side of capacitor C ₁ is switched to
+5V and the negative side is connected to
ground.
Phase 3
— V_DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C₁ produces –5V in the
negative terminal of C₁, which is applied to
the negative side of capacitor C₂. Since C₂₊ is
at +5V, the voltage potential across C₂ is l0V.
Phase 4
— V_DD transfer — The fourth phase of the
clock connects the negative terminal of C₂ to
ground,
and transfers the generated l0V across C₂ to
C₄, the V_DD storage capacitor. Again, simulta-
neously
with this, the positive side of capacitor C₁ is
switched to +5V and the negative side is
connected to ground, and the cycle begins
again.
Since both V⁺ and V^– are separately generated
from V_CC; in a no–load condition V⁺ and V^–
will
be symmetrical. Older charge pump ap-
proaches that generate V^– from V⁺ will show
a decrease in the magnitude of V^– compared
to V⁺ due to the inherent inefficiencies in the
design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors
can be as low as 0.1µF with a 16V breakdown
voltage rating.
V_CC = +5V
+
C_{1 –}
+
C_{2 –}
–10V
C₄
+ – V_DD Storage Capacitor
– + _{VSS Storage Capacitor}
C₃
Figure 2. Charge Pump — Phase 2
V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 1. Charge Pump — Phase 1
10V
C2+
GND
GND
C2-
-10V
Rev. 07/26/02
Figure 3. Charge Pump Waveforms
SP385E-1 True +3V to +5V RS-232 Line Driver/Receiver
6
© Copyright 2002 Sipex Corporation