SP202E Datasheet, PDF (6/15 Pages) Sipex Corporation – High-Performance RS-232 Line Drivers/Receivers

V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 4. Charge Pump — Phase 1
In actual system applications, it is quite possible
for signals to be applied to the receiver inputs
before power is applied to the receiver circuitry.
This occurs, for example, when a PC user attempts
to print, only to realize the printer wasn’t turned on.
In this case an RS-232 signal from the PC will
appear on the receiver input at the printer. When
the printer power is turned on, the receiver will
operate normally. All of these enhanced devices
are fully protected.
Charge Pump
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach com-
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 10V power supplies. There
is a free–running oscillator that controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— V_SS charge storage —During this phase of
the clock cycle, the positive side of capacitors
Ctthra_{1ennasnsfdewriCrtec2dhaetrdoetCoin2gi–}tr.ioaSullniyndccaehnaCdrg_2th+eediscthocaor+gn5enVein.ctCCed_l1+–
is
is
to
+5V, the voltage potential across capacitor C₂ is
now 10V.
Phase 2
— V_SS transfer — Phase two of the clock con-
nects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to ground, and transfers the generated –l0V to
C₃. Simultaneously, the positive side of capaci-
tor C ₁ is switched to +5V and the negative side
is connected to ground.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –5V in the negative
terminal of C₁, which
side of capacitor C₂.
is applied
Since C₂₊
to
is
the negative
at +5V, the
voltage potential across C₂ is l0V.
Phase 4
— V_DD transfer — The fourth phase of the clock
connects the negative terminal of C₂ to ground,
and transfers the generated l0V across C₂ to C₄,
the V_DD storage capacitor. Again, simultaneously
with this, the positive side of capacitor C₁ is
switched to +5V and the negative side is con-
nected to ground, and the cycle begins again.
Since both V⁺ and V^– are separately generated
from V_CC; in a no–load condition V⁺ and V^– will
V_CC = +5V
+
C_{1 –}
+
C_{2 –}
–10V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 5. Charge Pump — Phase 2
Rev. 06/20/02
SP202E Series High Performance RS232 Transceivers
6
© Copyright 2002 Sipex Corporation