SP6652 Datasheet, PDF (5/11 Pages) Sipex Corporation – 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

DETAIL DESCRIPTION
Current Mode Control and Slope
Compensation
The SP6652 is designed to use low value ce-
ramic capacitors and low value inductors, to
reduce the converter’s volume and cost in por-
table devices Current mode PWM control was,
therefore, chosen for the ease of compensation
when using ceramic output capacitors and better
transient line rejection, which is important in
battery powered applications. Current mode
control spreads the two poles of the output
power train filter far apart so that the modulator
gain crosses over at -20dB/decade instead of
the usual -40dB/decade. The external compen-
sation network is, simply, a series RC connected
between ground and the output of the internal
transconductance error amplifier.
It is well known that an unconditional instability
exists for any fixed frequency current-mode
converter operating above 50% duty cycle. A
simple, constant-slope compensation is chosen
to achieve stability under these conditions. The
most common high duty cycle application is a
Li-Ion battery powered regulator with a 3.3V
output (D ≥ 90%). Since the current loop is
critically damped when the compensation slope
(denoted MC_V) equals the negative discharge
slope (denoted M2_V), the amount of slope com-
pensation chosen is, therefore:
M2 = dI_L/dT_OFF =-V_OUT/L = -3.3V/4.7µH =
-702mA/µs
keep the effective current slope compensation
constant (remembering current is being com-
pensated, not voltage) the voltage slope must be
proportional to R_PMOS. To account for this, the
slope compensation voltage is internally gener-
ated with a bias current that is also proportional
to R_PMOS.
Over Current Protection
In steady state closed loop operation the voltage
at the COMP pin controls the duty cycle. Due to
the current mode control and the slope compen-
sation, this voltage will be:
V(COMP) (I_LPK* R_PMOS + MC_V *T_ON+ V_BE(Q1)
The COMP node will be clamped when the its
voltage tries to exceed V(BLIM) + V_BE (Q1).
The V_BE(Q1) term is cancelled by V_BE(Q2) at
the output of the translator. The correct value of
clamp voltage is, therefore:
V(BLIM) = IL(MAX)* RPMOS + MCV *tON
The I_L(MAX) term is generated with a bias current
that is proportional to R_PMOS, to keep the value
of current limit approximately constant over
process and temperature variations, while the
MC_V *T_ON is generated by a peak-holding cir-
cuit that senses the amplitude of the slope com-
pensation ramp at the end of T_ON.
M2_V = M2*R_PMOS
MC_V = -M2_V = 702mA/µs*0.2Ω = 140mV/µs,
for RPMOS = 0.20Ω
The inductor current is sensed as a voltage
across the PMOS charging switch and the NMOS
synchronous rectifier (see BLOCK DIAGRAM)
During inductor current charge, V(PVIN)-V(LX)
represents the charging current ramp times the
resistance of the PMOS charging switch. To
There is minimum on-time (T_ON) generated
even if the COMP node is at 0V, since the peak
current comparator is reset at the end of a charge
cycle and is held low during a blanking time
after the start of the next charge cycle. This is
necessary to swamp the transients in the induc-
tor current ramp around switching times. The
minimum T_ON (50ns, nominally) is not suffi-
cient for the COMP node to keep control of the
current when the output voltage is low. The
inductor current tends to rise until the energy
loss from the discharge resistances are equal to
Date:5/25/04
SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator
5
© Copyright 2004 Sipex Corporation