SP6339 Datasheet, PDF (5/13 Pages) Sipex Corporation – Triple μPower Supervisory Circuit with Manual Reset and Watchdog

PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
Name
V1
V2
WDI
V3
WDOB
GND
MRIB
RSTB
Description
First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
Second supply voltage input. Trip threshold voltage internally set.
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. RSTB output is
used to signal watchdog timeout overflow -- RSTB output pulses
high/low (depending on the active reset polarity) for the reset timeout
period after each watchdog timeout overflow. WDOB remains at
“LOW” logic level after watchdog timeout period is expired and it
remains “LOW” until WDI makes a transition. RSTB output is not
affected by the watchdog functionality. The watchdog timer clears
whenever the reset is asserted or manual reset is asserted or a
transition is observed at WDI pin.
Input for the third supply voltage. Trip threshold is 0.5V.
Watch Dog Output. Open-Drain or CMOS, active LOW. If WDI
remains at “HIGH” or “LOW” logic level for longer than the
watchdog timeout period, the internal watchdog timer overflows and
WDOB is asserted. WDOB does not de-assert until the watchdog is
cleared via transition at the WDI pin. Another scenario for WDOB to
assert is when the reset output is asserted due to an under-voltage V1,
V2, V3 condition. WDO de-asserts without a reset timeout period.
Floating WDI will not disable watchdog timer in devices with dedicated
WDOB output. Open-drain WDOB outputs require an external pull-up
resistor. CMOS outputs are referenced to V1.
Common ground reference pin.
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
Reset output. Open-Drain or CMOS, active low. Reset is asserted
when any of the three supply inputs is below its trip threshold. It stays
asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RSTB asserts when V1 or V2 or V3 drop below their
corresponding reset thresholds, or MRIB is pulled “LOW”. RSTB
remains asserted for the reset timeout period after V1 and V2 and V3
exceed their corresponding reset thresholds or MRIB goes “LOW”
to “HIGH”. Open-drain outputs require an external pull-up resistor.
CMOS outputs are referenced to V1.
Nov 20-06 Rev J
SP6339-SP6341 Triple µPower Supervisory Circuit
5
© Copyright 2006 Sipex Corporation