SP3483_04 Datasheet, PDF (5/9 Pages) Sipex Corporation – +3.3V Low Power Slew Rate Limited Half-Duplex RS-485 Transceiver

D
VCC
R
VOD
R
VOC
Figure 1. Driver DC Test Load Circuit
CL
D
GENERATOR
(NOTE 1)
50Ω
VCC
RL =
60Ω
OUT
CL = 15pF (NOTE 2)
Figure 3. Driver Differential Output Delay and Transition
Time Circuit
VDM
S1
D
GENERATOR
(NOTE 1)
50Ω
VCC
RL = 27Ω
OUT
CL = 15pF
(NOTE 2)
VOM =
VOH + VOL
2
1.5V
Figure 2. Driver Propagation Delay Test Circuit
GENERATOR
(NOTE 1)
S1
D
CL = 50pF
(NOTE 2)
50Ω
OUT
RL = 110Ω
VOM =
VOH + VOL
2
1.5V
Figure 4. Driver Enable and Disable Timing Circuit,
Output HIGH
0V OR 3V
S1
D
GENERATOR
(NOTE 1)
CL = 50pF
(NOTE 2)
50Ω
VCC
RL = 110Ω
OUT
Figure 5. Driver Enable and Disable Timing Circuit,
Output LOW
GENERATOR
(NOTE 1)
50Ω
VID
R
OUT
CL = 15pF
(NOTE 2)
1.5V
VOM = VCC
0V
2
Figure 6. Receiver Propagation Delay Test Circuit
1.5V
-1.5V
S3
VID
R
GENERATOR
(NOTE 1)
50Ω
1k
CL = 15pF
(NOTE 2)
S1
VCC
S2
Figure 7. Receiver Enable and Disable Timing Circuit
Date: 6/23/04
SP3483 Low Power Slew Rate Limited Half-Duplex RS485 Transceivers
5
© Copyright 2004 Sipex Corporation