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SP488E Datasheet, PDF (3/10 Pages) Sipex Corporation – Enhanced Quad RS-485/RS-422 Line Receivers | |||
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A
DI DRIVER
B
1/4 SP486E
100pF EN
54â¦
RCVR
100pF
EN
1/4 SP488E
ROn
CL
RCVR
CL
S1
1kâ¦
S2
1kâ¦
VCC
Figure 1. Timing Test Circuit
Figure 2. Enable/Disable Timing Test Circuit
SP488 PINOUT
Pin 1 â RI1B â Receiver 1 input B.
Pin 2 â RI A Receiver 1 input A.
1â
Pin 3 â RO1 â Receiver 1 Output â If
Receiver 1 output is enabled, if RI1A > RI1B by
200mV, Receiver output is high. If Receiver 1
output is enabled, and if RI A< RI B by 200mV,
1
1
Receiver 1 output is low.
Pin 4 â EN â Receiver Output Enable. Please
refer to SP488E Truth Table (1).
Pin 5 â RO2 â Receiver 2 Output â
If Receiver 2 output is enabled, if RI2A > RI2B
by 200mV, Receiver 2 output is high. If
Receiver 2 output is enabled, and if RI2A < RI2B
by 200mV, Receiver 2 output is low.
PINOUT
Pin 6 â RI A â Receiver 2 input A.
2
Pin 7 â RI2B â Receiver 2 input B.
Pin 8 â GND â Digital Ground.
Pin 9 â RI3B â Receiver 3 input B.
Pin 10 â RI3A â Receiver 3 input A.
Pin 11 â RO3 â Receiver 3 Output â If
Receiver 3 output is enabled, if RI A > RI B by
3
3
200mV, Receiver 3 output is high. If Receiver 3
output is enabled, and if RI3A < RI3B by 200mV,
Receiver 3 output is low.
Pin 12 â EN â Receiver Output Enable. Please
refer to SP488E Truth Table (1).
RI1B 1
RI1A 2
1
RO1 3
EN 4
RO2 5
RI2A 6
2
RI2B 7
GND 8
SP488E 16 VCC
15 RI4B
4
14 RI4A
13 RO4
12 EN
11 RO3
3
10 RI3A
9 RI3B
RI1B 1
RI1A 2
1
RO1 3
EN1/EN2 4
RO2 5
RI2A 6
2
RI2B 7
GND 8
SP489E 16 VCC
15 RI4B
4
14 RI4A
13 RO4
12 EN3/EN4
11 RO3
3
10 RI3A
9 RI3B
SP488E/489EDS/07
SP488E/489E Enhanced Quad RS-485/RS-422 Line Receivers
3
© Copyright 2000 Sipex Corporation
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