SP488 Datasheet, PDF (3/6 Pages) Sipex Corporation – Quad RS-485/RS-422 Line Receivers

A
DI DRIVER
B
1/4 SP486
100pF EN
54Ω
RCVR
100pF
EN
1/4 SP488
ROn
C_L
Figure 1. Timing Test Circuit
RCVR
C_L
S₁
1kΩ
S₂
1kΩ
V_CC
Figure 2. Enable/Disable Timing Test Circuit
SP488 PINOUT
Pin 1 — RI₁B — Receiver 1 input B.
Pin 2 — RI A Receiver 1 input A.
1—
Pin 3 — RO₁ — Receiver 1 Output — If Re-
ceiver 1 output is enabled, if RI₁A > RI₁B by
200mV, Receiver output is high. If Receiver 1
output is enabled, and if RI A< RI B by 200mV,
1
1
Receiver 1 output is low.
Pin 4 — EN — Receiver Output Enable. Please
refer to SP488 Truth Table (1).
Pin 5 — RO₂ — Receiver 2 Output — If Re-
ceiver 2 output is enabled, if RI₂A > RI₂B by
200mV, Receiver 2 output is high. If Receiver 2
output is enabled, and if RI₂A < RI₂B by
200mV, Receiver 2 output is low.
PINOUT
Pin 6 — RI A — Receiver 2 input A.
2
Pin 7 — RI₂B — Receiver 2 input B.
Pin 8 — GND — Digital Ground.
Pin 9 — RI₃B — Receiver 3 input B.
Pin 10 — RI₃A — Receiver 3 input A.
Pin 11 — RO₃ — Receiver 3 Output — If
Receiver 3 output is enabled, if RI A > RI B by
3
3
200mV, Receiver 3 output is high. If Receiver 3
output is enabled, and if RI₃A < RI₃B by
200mV, Receiver 3 output is low.
Pin 12 — EN — Receiver Output Enable. Please
refer to SP488 Truth Table (1).
RI₁B 1
RI₁A 2
1
RO₁ 3
EN 4
RO₂ 5
RI₂A 6
2
RI₂B 7
GND 8
SP488 ^{16 V}CC
15 RI₄B
4
14 RI₄A
13 RO₄
12 EN
11 RO₃
3
10 RI₃A
9 RI₃B
RI₁B 1
RI₁A 2
1
RO₁ 3
EN₁/EN₂ 4
RO₂ 5
RI₂A 6
2
RI₂B 7
GND 8
SP489 ^{16 V}CC
15 RI₄B
4
14 RI₄A
13 RO₄
12 EN₃/EN₄
11 RO₃
3
10 RI₃A
9 RI₃B
SP488/489
Quad RS-485/RS-422 Line Receivers
3
© Copyright 2000 Sipex Corporation